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参数资料
| 型号： | DS1372 |
| 厂商： | Maxim Integrated Products, Inc. |
| 元件分类： | 通用总线功能 |
| 英文描述： | I2C, 32-Bit, Binary Counter Clock with 64-Bit ID |
| 中文描述： | I²C、32位、二进制计数时钟，具有64位ID |
| 文件页数： | 3/12页 |
| 文件大小： | 173K |
| 代理商： | DS1372 |
D
_______________________________________________________________________________________
3
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Limits at -40°C are guaranteed by design and not production tested.
All voltages are referenced to ground.
SCL clocking at maximum frequency = 400kHz.
Specified with I
2
C bus inactive, SCL = SDA = V
CC
.
Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
The I
2
C minimum operating frequency is imposed by the requirement of timeout period.
The first clock pulse is generated after this period.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V
IHMIN
of the SCL sig-
nal) to bridge the undefined region of the falling edge of SCL.
The maximum t
HD:DAT
must only be met if the device does not stretch the low period (t
LOW
) of the SCL signal.
Note 10:
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
≥
250ns must then be met.
This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch
the low period of the SCL signal, it must output the next data bit to the SDA line t
R(MAX)
+ t
SU:DAT
= 1000 + 250 = 1250ns
before the SCL line is released.
Note 11:
C
B
= Total capacitance of one bus line in pF.
Note 12:
The parameter t
OSF
is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
2.4V
≤
V
CC
≤
V
CC(MAX)
.
Note 13:
The DS1372 can detect any single SCL clock held low longer than T
_TIMEOUT
(MIN). The I
2
C interface is in reset state and
can receive a new START condition when SCL is held low for at least T
_TIMEOUT
(MAX). Once the part detects this condi-
tion the SDA output is released. The oscillator must be running for this function to work.
Note 9:
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.4V to 5.5V, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
100
250
20 +
0.1C
B
20 +
0.1C
B
20 +
0.1C
B
20 +
0.1C
B
0.6
4.0
TYP
MAX
UNITS
Fast mode
Standard mode
Data Setup Time (Note 10)
t
SU:DAT
ns
Fast mode
300
Rise Time of SDA and SCL
Signals (Note 11)
t
R
Standard mode
1000
ns
Fast mode
300
Fall Time of SDA and SCL Signals
(Note 11)
t
F
Standard mode
300
ns
Fast mode
Standard mode
Setup Time for STOP Condition
t
SU:STO
μs
Capacitive Load for Each Bus
Line (Note 11)
I/O Capacitance
SCL Spike Suppresion
Oscillator Stop Flag (OSF) Delay
(Note 12)
Timeout Interval (Note 13)
C
B
400
pF
C
I/O
TSP
10
30
pF
ns
t
OSF
100
ms
T
_TIMEOUT
25
35
ms
CRYSTAL SPECIFICATIONS
PARAMETER
SYMBOL
f
O
C
L
ESR
MIN
TYP
32.768
12.5
MAX
UNITS
kHz
pF
k
Nominal Frequency
Capacitive Load
Equivalent Series Resistance
50
I
2
C, 32-Bit, Binary Counter Clock with 64-Bit ID
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