参数资料
型号: DS1372U+T&R
厂商: Maxim Integrated Products
文件页数: 10/12页
文件大小: 0K
描述: IC BINARY COUNTER 32-BIT 8-USOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 3,000
类型: 二进制计数器
特点: 警报器,方波输出,监视计时器
时间格式: 二进制
数据格式: 二进制
接口: I²C,2 线串口
电源电压: 2.4 V ~ 5.5 V
电压 - 电源,电池: 1.3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-uMAX
包装: 带卷 (TR)
Control Register (07h)
Bit 7: Enable Oscillator (EOSC). When set to logic 0,
the oscillator is started. When set to logic 1, the oscilla-
tor is stopped. This bit is clear (logic 0) when power is
first applied.
Bit 6: Alarm Counter Enable (ACE). When set to logic
1, the alarm counter is enabled. If alarm counter seed
register has a nonzero value, the counter runs and sets
the AF bit to 1 when the counter reaches 0. When set to
logic 0, the alarm counter is disabled, and the counter
can be used as RAM. This bit is clear (logic 0) when
power is first applied.
Bit 3: Interrupt Control (INTCN). This bit controls the
SQW/INT signal. When the INTCN bit is set to logic 0, a
square wave is output on the SQW/INT pin whose fre-
quency is defined by bits RS2 and RS1, according to
Table 2. The oscillator must also be enabled for the
square wave to be output. When the INTCN bit is set to
logic 1, this permits the AF bit in the Status Register to
assert SQW/INT (provided that ACE and AIE are also
enabled) whenever AF = 1. If ACE = 1, the alarm flag is
always set on an alarm condition, regardless of the
state of the INTCN bit. The INTCN bit is set to logic 1
when power is first applied.
Bits 2 and 1: Rate Select (RS[2:1]). These bits control
the frequency of the square-wave output when the
square wave has been enabled. Table 2 shows the
square-wave frequencies that can be selected with the
RS bits. These bits are both set (logic 1) when power is
first applied.
Bit 0: Alarm Interrupt Enable (AIE). When set to a
logic 1, this bit permits the alarm flag (AF) to assert
SQW/INT (when INTCN = 1). The AIE bit is disabled
(logic 0) when power is first applied.
Table 2. Square-Wave/Interrupt Output
Frequencies
Note: When interrupt operation is enabled, the SQW/INT out-
put is the inverse of the AF bit.
Bit #
7
6
5
4
3
2
1
0
Name
EOSC
ACE
0
INTCN
RS2
RS1
AIE
Reset
0
1
0
Control Register (07h)
DS1372
_______________________________________________________________________________________
7
Special Purpose Registers
The DS1372 has two additional registers that control
the alarm counter and interrupts: Control Register (07h)
and Status Register (08h).
INTCN
ACE
AIE
RS2
RS1
SQW/
INT
OUTPUT
0
X
0
1Hz
0
X
0
1
4.096kHz
0
X
1
0
8.192kHz
0
X
1
32.768kHz
1
X
Interrupt
I2C, 32-Bit, Binary Counter Clock with 64-Bit ID
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