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参数资料
| 型号： | DS1384FP-12+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 14/18页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR RTC WDOG 120NS 44-MQFP |
| 标准包装： | 96 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年，方波输出，监视计时器 |
| 存储容量： | 50B |
| 时间格式： | HH:MM:SS:hh（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电压 - 电源，电池： | 2.4 V ~ 4 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-QFP |
| 供应商设备封装： | 44-MQFP（10x10） |
| 包装： | 托盘 |
DS1384
5 of 18
contention. However, if the output bus has been enabled (
CE and OE active), then WE will disable the
outputs in tWEZ from its falling edge.
When the address value presented to the DS1384 during the write is in the range of 00000H through
0003FH, one of the 64 on-chip registers will be selected and data will be written into the device.
When the address value presented to the DS1384 during the write is in the range of 00040H through
1FFFFH, an external SRAM location will be selected.
DATA RETENTION MODE
When VCCI is within nominal limits (VCC > 4.5V) the DS1384 can be accessed as described above with
read or write cycles. However, when VCC is below the power-fail point, VPF, (point at which write
protection occurs) the internal clock registers and external RAM is blocked from access. This is
accomplished internally by inhibiting access to the clock registers via the
CE signal. At this time the
power fail output signal (
PFO) is driven active and will remain active until VCC returns to nominal levels.
External RAM access is inhibited in a similar manner by forcing
CEO to high level. This level is within
0.2 volts of the VCCI input. CEO will remain at this level as long as VCCI remains at an out-of-tolerance
condition. When VCCI falls below the level of the battery (VBAT1 or VBAT2), power input is switched from
the VCCI pin to the VBAT pin and the clock registers are maintained from the attached battery supply.
External RAM is also powered by the VBAT input when VCCI is below VBAT pin through the VCCO pin. The
VCCO pin is capable of supplying 100A of current to the attached memory with less than 0.3V drop
under this condition. On power-up, when VCCI returns to in-tolerance conditions, write protection
continues for 150ms by inhibiting
CEO. The PFO signal also remains active during this time. The
DS1384 is capable of supporting two batteries which are used in a redundant fashion for applications
which require added reliability or increased battery capacity. When two batteries are used, the higher of
the two is selected for use. A selected battery will remain as backup supply until it is significantly below
the other. When the selected battery voltage falls below the alternate battery by about 0.6V, the alternate
battery is selected and then becomes the backup supply. This switching occurs transparently to the user
and continues until both batteries are exhausted. When only a single battery is required, both battery
inputs can be connected together. However, a more effective method of using a single battery supply is to
ground the unused battery input. When using a single battery, VBAT1 is the preferred input.
WATCHDOG TIMEKEEPER REGISTERS
The DS1384 Watchdog Timekeeper Controller has 14 internal registers, which are 8 bits wide and
contain all of the Timekeeping, Alarm, Watchdog, Control, and Data information. The Clock, Calendar,
Alarm and Watchdog Registers are memory locations, which contain external (user accessible) and
internal copies of the data. The external copies are independent of internal functions except that they are
updated periodically by the simultaneous transfer of the incremented internal copy (see Figure 1). The
Command Register bits are affected by both internal and external functions. This register will be
discussed later. The 50 bytes of RAM registers are accessed from the external address and data bus and
reside or overlay external static RAM. Registers 0, 1, 2, 4, 6, 8, 9 and A contain time of day and date
information (see Figure 2). Time of day information is stored in BCD. Registers 3, 5, and 7 contain the
time of day alarm information. Time of day alarm information is stored in BCD. Register B is the
Command Register and information in this register is binary. Register C and D are the Watchdog Alarm
Registers and information, which is stored in these two registers, is in BCD. Registers 0000EH through
register 0003FH are on-chip user bytes and can be used to contain data at the user’s discretion.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1384FP-12+ | 功能描述:实时时钟 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| DS1384FP-120 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| DS1384T-120 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| DS1384T-150 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| DS1385 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:RAMified Real Time Clock 4K x 8 |
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