参数资料
型号: DS1388Z-3+T&R
厂商: Maxim Integrated Products
文件页数: 7/19页
文件大小: 0K
描述: IC RTC I2C W/CHARGER 8-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 时钟/日历
特点: EEPROM,闰年,监控器,涓流充电器,监视计时器
存储容量: 512B
时间格式: HH:MM:SS:hh(12/24 小时)
数据格式: YY-MM-DD-dd
接口: I²C,2 线串口
电源电压: 2.7 V ~ 3.3 V
电压 - 电源,电池: 1.3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
Maxim Integrated
15
DS1388
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number
of data bytes transferred between the START and the
STOP conditions is not limited, and is determined by
the master device. The information is transferred
byte-wise and each receiver acknowledges with a
ninth bit.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
(ACK) after the reception of each byte. The master
device must generate an extra clock pulse, which is
associated with this acknowledge bit. The DS1388
does not generate any acknowledge bits if access to
the EEPROM is attempted during an internal pro-
gramming cycle.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by generating a not-acknowledge (NACK) bit on
the last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
Figures 7 and 8 detail how data transfer is accom-
plished on the I2C bus. Depending upon the state of
the R/W bit, two types of data transfer are possible:
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte. Data are transferred with the
most significant bit (MSB) first.
Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last
received byte, a NACK is returned.
The master device generates all the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a repeat-
ed START condition. Since a repeated START
condition is also the beginning of the next serial
transfer, the bus is not released. Data are transferred
with the most significant bit (MSB) first.
SDA
SCL
IDLE
1–7
8
9
1–7
8
9
1–7
8
9
START
CONDITION
STOP CONDITION
REPEATED START
SLAVE
ADDRESS
R/W
ACK
DATA
ACK/
NACK
DATA
MSB FIRST
MSB
LSB
MSB
LSB
REPEATED IF MORE BYTES
ARE TRANSFERRED
Figure 6. I2C Data Transfer Overview
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