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参数资料
| 型号： | DS14285QN |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | Timer or RTC |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 7/25页 |
| 文件大小： | 303K |
| 代理商： | DS14285QN |
DS14285/DS14287
15 of 25
PERIODIC INTERRUPT RATE AND
SQUARE WAVE OUTPUT FREQUENCY Table 2
SELECT BITS REGISTER A
RS3
RS2
RS1
RS0
tPI PERIODIC
INTERRUPT RATE
SQW OUTPUT
FREQUENCY
0
None
0
1
3.90625 ms
256 Hz
0
1
0
7.8125 ms
128 Hz
0
011
122.070
s
8.192 kHz
0
100
244.141
s
4.096 kHz
0
101
488.281
s
2.048 kHz
0
110
976.5625
s
1.024 kHz
0
1
1.953125 ms
512 Hz
1
0
3.90625 ms
256 Hz
1
0
1
7.8125 ms
128 Hz
1
0
1
0
15.625 ms
64 Hz
1
0
1
31.25 ms
32 Hz
1
0
62.5 ms
16 Hz
1
0
1
125 ms
8 Hz
1
0
250 ms
4 Hz
1
500 ms
2 Hz
UPDATE CYCLE
The DS14285/DS14287 executes an update cycle once per second regardless of the SET bit in Register B.
When the SET bit in Register B is set to one, the user copy of the double buffered time, calendar, and
alarm bytes is frozen and will not update as the time increments. However, the time countdown chain
continues to update the internal copy of the buffer. This feature allows time to maintain accuracy
independent of reading or writing the time, calendar, and alarm buffers and also guarantees that time and
calendar information is consistent. The update cycle also compares each alarm byte with the
corresponding time byte and issues an alarm if a match or if a “don’t care” code is present in all three
positions.
There are three methods that can handle access of the real-time clock that avoid any possibility of
accessing inconsistent time and calendar data. The first method uses the update-ended interrupt. If
enabled, an interrupt occurs after every up date cycle that indicates that over 999 ms are available to read
valid time and date information. If this interrupt is used, the IRQF bit in Register C should be cleared
before leaving the interrupt routine.
A second method uses the update-in-progress bit (UIP) in Register A to determine if the update cycle is in
progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs
244
s later. If a low is read on the UIP bit, the user has at least 244 s before the time/calendar data will
be changed. Therefore, the user should avoid interrupt service routines that would cause the time needed
to read valid time/calendar data to exceed 244
s.
The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in
Register A is set high between the setting of the PF bit in Register C (see Figure 4). Periodic interrupts
that occur at a rate of greater than tBUC allow valid time and date information to be reached at each
occurrence of the periodic interrupt. The reads should be complete within 1 (tPI/
2
+ tBUC) to ensure that
data is not read during the update cycle.
相关PDF资料 |
PDF描述 |
|---|---|
| DS14285S | 1 TIMER(S), REAL TIME CLOCK, PDSO24 |
| DS14285N | 1 TIMER(S), REAL TIME CLOCK, PDIP24 |
| DS14285SN | 1 TIMER(S), REAL TIME CLOCK, PDSO24 |
| DS14285Q | 1 TIMER(S), REAL TIME CLOCK, PQCC28 |
| DS14285 | 1 TIMER(S), REAL TIME CLOCK, PDIP24 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS14285QN+ | 功能描述:实时时钟 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| DS14285S | 功能描述:实时时钟 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| DS14285S/T&R | 制造商:Maxim Integrated Products 功能描述:IC RTC W/NV RAM CNTRL 24-SOIC |
| DS14285S/T&R | 功能描述:实时时钟 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| DS14285S/TR | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:Real-Time Clock with NV RAM |
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