参数资料
型号: DS14285SN+T&R
厂商: Maxim Integrated Products
文件页数: 21/26页
文件大小: 0K
描述: IC RTC W/NV RAM CNTRL 24-SOIC
标准包装: 1,000
类型: 时钟/日历
特点: 警报器,夏令时,闰年,NVSRAM,方波输出
存储容量: 114B
时间格式: HH:MM:SS(12/24 小时)
数据格式: YY-MM-DD-dd
接口: 并联
电源电压: 4.5 V ~ 5.5 V
电压 - 电源,电池: 2.5 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC W
包装: 带卷 (TR)
DS14285/DS14287
4 of 26
MOT (Mode Select) - The MOT pin offers the flexibility to choose between to bus types. When
connected to VCC, Motorola bus timing is selected. When connected to GND or left disconnected, Intel
bus timing is selected. The pin has an internal pull-down resistance of approximately 20 K
. This pin is
on the DS14285Q only.
AS (Address Strobe Input) - A positive going address strobe pulse serves to demultiplex the bus. The
falling edge of AS/ALE causes the address to be latched within the DS14285/DS14287.
DS (Data Strobe or Read Input) - For the DS14285Q the DS/ RD pin has two modes of operation
depending on the level of the MOT pin. When the MOT pin is connected to VCC, Motorola bus timing is
selected. In this mode DS is a positive pulse during the latter portion of the bus cycle and is called Data
Strobe. During read cycles, DS signifies the time that the DS14285Q is to drive the bidirectional bus. In
write cycles the trailing edge of DS causes the DS14285Q to latch the written data. When the MOT pin is
connected to GND, Intel bus timing is selected. In this mode the DS pin is called Read( RD ). RD identifies
the time period when the DS14285Q drives the bus with read data. The RD signal is the same definition
as the Output Enable ( OE ) signal on a typical memory.
The DS14285, DS14285S and DS14287 do not have a MOT pin and therefore operate only in Intel bus
timing mode.
R/ W (Read/Write Input) - The R/ W pin also has two modes of operation. When the MOT pin is
connected to VCC for Motorola timing, R/ W is at a level which indicates whether the current cycle is a
read or write. A read cycle is indicated with a high level on R/ W while DS is high. A write cycle is
indicated when R/ W is low during DS.
When the MOT pin is connected to GND for Intel timing, the R/ W signal is an active low signal called
WR
. In this mode the R/ W pin has the same meaning as the Write Enable signal ( WE ) on generic
RAMs.
CS
(Chip Select Input) - The Chip Select signal must be asserted low for a bus cycle in the
DS14285/DS14287 to be accessed. CS must be kept in the active state during DS for Motorola timing
and during RD and WR for Intel timing. Bus cycles which take place without asserting CS will latch
addresses but no access will occur. When VCC is below 4.25 volts, the DS14285/DS14287 internally
inhibits access cycles by internally disabling the CS input. This action protects both the real time clock
data and RAM data during power outages.
IRQ
(Interrupt Request Output) - The IRQ pin is an active low output of the DS14285/DS14287 that
can be used as an interrupt input to a processor. The IRQ output remains low as long as the status bit
causing the interrupt is present and the corresponding interrupt-enable bit is set. To clear the IRQ pin the
processor program normally reads the C register. The RESET pin also clears pending interrupts.
When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple
interrupting devices can be connected to an IRQ bus. The IRQ bus is an open drain output and requires an
external pull-up resistor.
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