参数资料
型号: DS1511
厂商: Maxim Integrated Products, Inc.
英文描述: Y2KC Watchdog Real Time Clock(Y2KC看门狗实时时钟)
中文描述: Y2K兼容、看门狗实时时钟
文件页数: 3/22页
文件大小: 178K
代理商: DS1511
DS1501/DS1511
071098 3/22
DS1501/DS1511 BLOCK DIAGRAM
Figure 1
CLWATCHDOG
COUNTDOWN
POWER CONTROL
WAND POWER–ON
RESET
16 x 8
CLOCK AND CONTROL
REGISTERS
256 x 8
NV SRAM
CE
WE
OE
RST
PWR
IRQ
SQW
A0–A4
DQ0–DQ7
32.768 kHz
CLOCK OSC
X1
X2
V
CC
V
BAT
V
BAUX
GND
KS
DS1501/DS1511 OPERATING MODES
Table 1
V
CC
CE
OE
WE
DQ0–DQ7
A0–A4
MODE
POWER
IN TOLERANCE
V
IH
X
X
HIGH–Z
X
DESELECT
STANDBY
V
IL
X
V
IL
D
IN
A
IN
WRITE
ACTIVE
V
IL
V
IL
V
IH
D
OUT
A
IN
READ
ACTIVE
V
IL
V
IH
V
IH
HIGH–Z
A
IN
READ
ACTIVE
V
BAT
< V
CC
< TOLERANCE
X
X
X
HIGH–Z
X
DESELECT
CMOS STANDBY
V
CC
< V
BAT
X
X
X
HIGH–Z
X
DATA
RETENTION
BATTERY
CURRENT
DATA READ MODE
The DS1501/DS1511 is in the read mode whenever CE
(chip enable) is low and WE (write enable) is high. The
device architecture allows ripple through access to any
valid address location. Valid data will be available at the
DQ pins within t
AA
(address access) after the last
address input is stable, providing that CE and OE
access times are satisfied. If CE or OE access times are
not met, valid data will be available at the latter of chip
enable access (t
CEA
) or at output enable access time
(t
OEA
). The state of the data input/output pins (DQ) is
controlled by CE and OE. If the outputs are activated
before t
AA
, the data lines are driven to an intermediate
state until t
AA
. If the address inputs are changed while
CE and OE remain valid, output data will remain valid for
output data hold time (t
OH
) but will then go indeterminate
until the next address access. (See Table 1.)
DATA WRITE MODE
The DS1501/DS1511 is in the write mode whenever WE
and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE.
The addresses must be held valid throughout the cycle.
CE and WE must return inactive for a minimum of t
WR
prior to the initiation of a subsequent read or write cycle.
Data in must be valid t
DS
(data setup) prior to the end of
the write and remain valid for t
DH
(data hold) afterward.
In a typical application, the OE signal will be high during
a write cycle. However, OE can be active provided that
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