参数资料
型号: DS1511
厂商: Maxim Integrated Products, Inc.
英文描述: Y2KC Watchdog Real Time Clock(Y2KC看门狗实时时钟)
中文描述: Y2K兼容、看门狗实时时钟
文件页数: 7/22页
文件大小: 178K
代理商: DS1511
DS1501/DS1511
071098 7/22
register values match alarm register settings, the Time
of Day/Date alarm Flag ‘TDF’ bit is set to logic 1. If TIE is
also set to logic 1, the alarm condition activates the IRQ.
NOTE: Please refer to Table 2 as required for the follow-
ing functional descriptions.
ALARM MASK BITS
Table 3
DY/DT
AM4
AM3
AM2
AM1
ALARM RATE
X
1
1
1
1
ONCE PER SECOND
X
1
1
1
0
WHEN SECONDS MATCH
X
1
1
0
0
WHEN MINUTES AND SECONDS MATCH
X
1
0
0
0
WHEN HOURS, MINUTES, AND SECONDS MATCH
0
0
0
0
0
WHEN DATE, HOURS, MINUTES, AND SECONDS MATCH
1
0
0
0
0
WHEN DAY, HOURS, MINUTES, AND SECONDS MATCH
USING THE WATCHDOG TIMER
The watchdog timer can be used to detect an out–of–
control processor. The user programs the watchdog
timer by setting the desired amount of time–out into the
two BCD Watchdog Registers (Address 0Ch and 0Dh).
(For example: writing 06h in the watchdog register 0Ch
and 00h to watchdog register 0Dh will set the watchdog
time–out to 60 milli–seconds). If the processor does not
access the timer, with a read or write, within the speci-
fied period, the Watchdog Flag ‘WDF’ is set and a pro-
cessor interrupt is generated at the IRQ pin or the RST
pin depending on the status of the Watchdog Steering
bit.
Bit 0 of register 0Fh is the Watchdog Steering Bit ‘WDS’.
When set to a 0, the watchdog will activate the IRQ out-
put when the watchdog times out. The WDF bit will be
set to a logic 1 to serve as an indication to the processor
that a watchdog reset has occurred.
When WDS is set to a 1, the watchdog will output a logic
low (0) pulse on the RST output for a duration of 40 ms to
200 ms. The Watchdog time–out will be restarted and
WDE (the Watchdog Enable) bit will reset to a logic 0 at
the beginning of a watchdog time–out when the WDS bit
is set to a logic 1. The WDF bit will remain set to a logic 1
to serve as an indication to the processor that a watch-
dog reset has occurred.
The watchdog timer resets when the processor per-
forms a read or write of the Watchdog register. The
time–out period then starts over. The watchdog timer is
disabled by writing a value of 00h to both watchdog reg-
isters. The watchdog functions are automatically dis-
abled upon power–up.
CLEARING IRQ AND FLAGS
The alarm flag(s), watchdog flag, and the IRQ output are
cleared by reading the Flags register (0Eh, bits 0–3) or
writing “0” to the corresponding Flag as shown in Fig-
ures 2a and 2b.
IRQ AND FLAG WAVEFORMS
Figure 2a
A0–A4
IRQ
ADDRESS 0Eh
15 ns MIN
HIGH–Z
OE
ACTIVE FLAG BIT(S)
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