DS1615
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Samples Counter. These two counters can be used to
guarantee that the DS1615 data has not been cleared at
any time during a given period of time. The Current
Samples Counter counts the number of samples that
have occurred since the most recent data acquisition
operation was started (i.e., the number of samples since
the Sample Rate register was written to a non–zero
value). The Total Samples Counter counts the total
number of samples that have been recorded in the life of
the device (assuming the lithium energy source has not
been removed during that time). If the end user knows
the value in the Total Samples Counter before the data
acquisition operation is started, he can guarantee that
the DS1615 has not been cleared. If the Current Sam-
ples count equals the difference between the ending
value and beginning value of the Total Samples
Counter, then the DS1615 data has not been cleared
during that time frame.
As a fourth security measure, changing any value in the
RTC and Control registers (with the exception of the
Status register) will stop datalogging and clear the Mis-
sion–in–Progress (MIP) bit.
SERIAL INTERFACE
The DS1615 provides two different serial communica-
tions options; asynchronous and synchronous.
The mode of communication is selected via the COM-
SEL pin. When this pin is pulled high, the DS1615 oper-
ates in synchronous mode. In this mode, communica-
tion with the DS1615 is facilitated by the SCLK, I/O, and
RST pins. When COMSEL is pulled low or floated,
asynchronous communications is selected and com-
munication with the device occurs over the TX and RX
pins. The operation of each mode is discussed in further
detail below.
Asynchronous Communication
In asynchronous mode, the DS1615 operates as a
slave peripheral device which is read and written over a
half duplex asynchronous data interface at the fixed rate
of 9,600 bits per second. Data is received and trans-
mitted in 8–bit bytes using a standard asynchronous
serial communications format as shown in Figure 3.
This format is easily generated by the UART in most
systems. The DS1615 data format implements 10 bit
words including one start bit, eight data bits, and one
stop bit. Data is received by the DS1615 on the RX pin
and transmitted by the TX pin.
COMMUNICATION WORD FORMAT
Figure 3
START
BIT
DATA
BIT
STOP
BIT
D0
D1
D2
D3
D4
D5
D6
D7
Synchronous Communication
Synchronous communication is accomplished over the
3–wire bus which is composed of three signals. These
are the RST (reset), the SCLK (serial clock), and I/O
(data I/O) pins. The 3–wire bus operates at a maximum
data rate of 2 Mbps. All data transfers are initiated by
driving the RST input high and are terminated by driving
RST low. (See Figures 6 and 7.) A clock cycle is a
sequence of a falling edge followed by a rising edge. For
data inputs, the data must be valid during the rising
edge. Data bits are output on the falling edge of the
clock and remain valid through the rising edge.
When reading data from the DS1615, the I/O pin goes to
a high impedance state when the clock is high. Taking
RST low will terminate any communication and cause
the I/O pin to go to a high impedance state.
General Communications Format
Communication with the DS1615 in both synchronous
and asynchronous modes is accomplished by first writ-
ing a command to the device. The command is then fol-
lowed by the parameters and/or data required by the
command. The command set for the DS1615 can be
seen in Table 3. Reads and writes to the DS1615 differ