参数资料
型号: DS16EV5110ASQX/NOPB
厂商: National Semiconductor
文件页数: 20/24页
文件大小: 0K
描述: IC EQUALIZER VIDEO 3D+C 48-LLP
产品培训模块: Signal Conditioning Applications
标准包装: 2,500
类型: 视频均衡器
应用: HD 显示器,DVI/HDMI
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-LLP(7x7)
包装: 带卷 (TR)
其它名称: DS16EV5110ASQX
SNLS301C – JULY 2008 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
N
Supply Noise Tolerance(3)
DC to 50MHz
100
mVP-P
CML INPUTS
VTX
Input Voltage Swing (Launch
Measured differentially at TPA
800
1200
mVP-P
Amplitude)
VICMDC
Input Common-Mode Voltage
DC-Coupled Requirement
VDD-0.3
VDD-0.2
V
Measured at TPA (Figure 2)
VIN
Input Voltage Swing
Measured differentially at TPB
120
mVP-P
RLI
Differential Input Return Loss
100 MHz– 825 MHz, with fixture's
10
dB
effect de-embedded
RIN
Input Resistance
IN+ to VDD and IN
to VDD
45
50
55
CML OUTPUTS
VO
Output Voltage Swing
Measured differentially with OUT+
and OUT
terminated by 50 to
800
1200
mVP-P
VDD
VOCM
Output common-mode Voltage
Measured Single-ended
VDD-0.3
VDD-0.2
V
IOFF
Output Leakage Current
VOUT = 3.6V, VDD = open or 0V
±1
A
tR, tF
Transition Time
20% to 80% of differential output
voltage, measured within 1" from
75
240
ps
output pins.
tCCSK
Inter Pair Channel-to-Channel
Difference in 50% crossing
Skew (all 4 Channels)
between shortest and longest
25
ps
channels
tD
Latency
350
ps
OUTPUT JITTER
TJ1
Total Jitter at 1.65 Gbps
20m 28 AWG STP DVI Cable
Data Paths
0.13
0.17
UIP-P
EQ Setting 0x04 PRBS7(4) (5) (6)
TJ2
Total Jitter at 2.25 Gbps
20m 28 AWG STP DVI Cable
Data Paths
0.2
UIP-P
EQ Setting 0x04 PRBS7(4) (5) (6)
TJ3
Total Jitter at 165 MHz
Clock Paths
0.165
UIP-P
Clock Pattern(4) (5) (6)
TJ4
Total Jitter at 225 MHz
Clock Paths
0.165
UIP-P
Clock Pattern(4) (5) (6)
RJ
Random Jitter
See (6) (7)
3
psrms
BIT RATE
FCLK
Clock Frequency
Clock Path(4)
25
225
MHz
BR
Bit Rate
Data Path(4)
0.25
2.25
Gbps
(3)
Allowed supply noise (mVP-P sine wave) under typical conditions.
(4)
Specification is ensured by characterization and is not tested in production.
(5)
Deterministic jitter is measured at the differential outputs (TPC of Figure 2), minus the deterministic jitter before the test channel (TPA of
Figure 2). Random jitter is removed through the use of averaging or similar means.
(6)
Total Jitter is defined as peak-to-peak deterministic jitter from () + 14.2 times random jitter in psrms.
(7)
Random jitter contributed by the equalizer is defined as sq rt (JOUT
2 J
IN
2). J
OUT is the random jitter at equalizer outputs in psrms, see
TPC of Figure 2; JIN is the random jitter at the input of the equalizer in psrms, see TPA of Figure 2.
Copyright 2008–2013, Texas Instruments Incorporated
5
Product Folder Links: DS16EV5110A
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