参数资料
型号: DS16EV5110ASQX/NOPB
厂商: National Semiconductor
文件页数: 4/24页
文件大小: 0K
描述: IC EQUALIZER VIDEO 3D+C 48-LLP
产品培训模块: Signal Conditioning Applications
标准包装: 2,500
类型: 视频均衡器
应用: HD 显示器,DVI/HDMI
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-LLP(7x7)
包装: 带卷 (TR)
其它名称: DS16EV5110ASQX
Input
Termination
Limiting
Amplifier
DC Offset Correction
Clock
Channel
EN
SMBus
REG3[3]
EN
Signal Detect Thresh.
SMBus Register
Signal Detect
SMBus Register
SD
C_OUT-
C_OUT+
C_IN-
C_IN+
SMBus
REG7[0]
SNLS301C – JULY 2008 – REVISED APRIL 2013
Figure 4. DS16EV5110A Clock Channel
OUTPUT LEVEL CONTROL
The output amplitude of the TMDS drivers for both the data channels and the clock channel can be controlled via
the SMBus (see Table 1). The default output level is 1000mV p-p. The following Table presents the output level
values supported:
Table 5. Output Level Control Settings – REG
0x08[3:2]
Bit 3
Bit 2
Output Level (mV)
0
540
0
1
770
1
0
1000 (default)
1
1200
AUTOMATIC ENABLE FEATURE
It may be desired for the DS16EV5110A to be configured to automatically enter STANDBY mode if no clock
signal is present. STANDBY mode can be implemented by connecting the Signal Detect (SD) pin to the external
(LVCMOS) Enable (EN) pin. In order for this option to function properly, REG07[0] should be set to a “0” (default
value). If the clock signal applied to the clock channel input swings above the SD_ON threshold specified in the
threshold register via the SMBus, then the SD pin is asserted High. If the SD pin is connected to the EN pin, this
will enable the equalizer, limiting amplifier, and output buffer on the data channels and the limiting amplifier and
output buffer on the clock channel; thus the DS16EV5110A will automatically enter the ACTIVE state. If the clock
signal present falls below SD_OFF threshold specified in the threshold register, then the SD pin will be asserted
Low, causing the aforementioned blocks to be placed in the STANDBY state.
12
Copyright 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS16EV5110A
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