参数资料
型号: DS1780E+
厂商: Maxim Integrated
文件页数: 10/28页
文件大小: 0K
描述: IC CPU PERIPHERAL MON 24-TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 62
功能: 温度监控器,CPU 外围设备
传感器类型: 内部
感应温度: -40°C ~ 125°C
精确度: ±12°C(最小值)
拓扑: ADC(三角积分型),比较器,风扇速度控制,寄存器库
输出类型: I²C?/SMBus?
输出警报:
输出风扇:
电源电压: 2.8 V ~ 5.75 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 管件
产品目录页面: 1436 (CN2011-ZH PDF)
DS1780
V MIN (V REF , R 1 , R 2 ) @ -
R 2
R 1
V REF
V MAX (V REF , R 1 , R 2 ) @ V REF -(V REF -3.6) é ê
ú
?
?
R 1 + R 2 ù
R 1
If the +2.5V S /+V CCP2 is to be used to monitor a secondary processor core voltage (V CCP2 ), R2 should be
removed and R1=500 ? . Table 6 below shows the voltage/data relationship for these inputs in the ideal
case. In this example, V REF =+5.0V, R1=4.0 k ? , and R2=23.2 k ? .
Analog inputs will provide best accuracy when referred to the GNDA pin. A separate, low-impedance
ground plane for analog ground, which provides a ground point for the voltage dividers and analog
components will provide best performance but is not mandatory. Analog components such as voltage
dividers should be located physically as close as possible to the DS1780.
The power supply bypass, the parallel combination of 10 μF (electrolytic or tantalum) and 0.1 μF
(ceramic) bypass capacitors connected between pin 9 and ground, should also be located as close as
possible to the DS1780.
VOLTAGE/DATA RELATIONSHIPS FOR V CCP VOLTAGE INPUTS
(+V CCP1 , +2.5VS/ +V CCP2 ) Table 6
INPUT PIN +V CCP1 +2.5V S /+V CCP2
LSb WEIGHTING (mV) 14.1 96.0
(Used to monitor V CCP )
(Used to monitor -12V)
ADC RESULT (BASE 10)
0
1
2
3
4
?
?
?
136
137
138
139
?
?
?
252
253
254
255
PIN VOLTAGE (V)
0
0.014
0.028
0.042
0.056
?
?
?
1.920
1.934
1.948
1.962
?
?
?
3.558
3.572
3.586
3.60
SUPPLY VOLTAGE (V)
-29.0
-28.90
-28.81
-28.71
-28.62
?
?
?
-15.94
-15.85
-15.75
-15.66
?
?
?
-4.808
-4.712
-4.616
-4.52
OPERATION - FAN Speed Data Format
Inputs are provided for signals from fans equipped with tachometer outputs. These are logic-level inputs
with an approximate threshold of 1.4V. Signal conditioning in the DS1780 accommodates the slow rise
and fall times typical of fan tachometer outputs. The maximum input signal range is 0 to V DD . In the
event these inputs are supplied from fan outputs which exceed 0 to V DD , either resistive division or diode
clamping must be included to keep inputs within an acceptable range, as shown in Figure 3. R2 is
selected so that it does not develop excessive voltage due to input leakage. R1 is selected based on R2 to
provide a minimum input of 2V and a maximum of V DD . R1 should be as low as possible to provide the
10 of 28
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