参数资料
型号: DS1780E+
厂商: Maxim Integrated
文件页数: 6/28页
文件大小: 0K
描述: IC CPU PERIPHERAL MON 24-TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 62
功能: 温度监控器,CPU 外围设备
传感器类型: 内部
感应温度: -40°C ~ 125°C
精确度: ±12°C(最小值)
拓扑: ADC(三角积分型),比较器,风扇速度控制,寄存器库
输出类型: I²C?/SMBus?
输出警报:
输出风扇:
电源电压: 2.8 V ~ 5.75 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 管件
产品目录页面: 1436 (CN2011-ZH PDF)
DS1780
2-WIRE SERIAL COMMUNICATION WITH THE DS1780 Figure 2
OPERATION - Power-on
Applying power to the DS1780 causes a reset of several of the registers. Power-on conditions of the
registers are shown in Table 2 above. Some registers have indeterminate power-on values, such as the
Limit and RAM registers of the Value RAM page, and these are not shown in the table. Upon power-up
the ADC is inactive. Writing Limits into the Value RAM should usually be the first action performed
after power up. The RST pin is bi-directional. It forces RESET at power-on, but can also be pulled low to
force RESET internally.
OPERATION - Resets
The DS1780 features four distinct resetting functions. Each one has a different effect on register contents
and the state of the RST output following the event. Each one is explained below:
Power-on Reset - On POR, all internal logic is reset, and registers are cleared to their default state (see
tables 10.x). Because Value RAM is typically the first area programmed upon power-up, it does not have
a defined state upon POR. Also, on POR, the RST output will be pulled to an active low state for 20 ms
(minimum).
A POR occurs every time V DD crosses the voltage level approximately equivalent to the sum of one n-
channel threshold (V TN ) and one p-channel threshold (V TP ), on a power-up or power-down condition.
DS1780 SRAM contents get “scrambled” when V DD falls below the greater of one n-channel V T or one p-
channel V T . Therefore, SRAM contents will always be in a defined state as supply voltage reaches the
minimum spec level of 2.8V, even in a power supply brownout condition.
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