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参数资料
| 型号： | DS1807S+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/13页 |
| 文件大小： | 0K |
| 描述： | IC POT ADDRESS 2X AUDIO 16-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 接片： | 64 |
| 电阻（欧姆）： | 45k |
| 电路数： | 2 |
| 温度系数： | 标准值 750 ppm/°C |
| 存储器类型： | 易失 |
| 接口： | I²C（芯片选择） |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 带卷 (TR) |
DS1807
12 of 13
110499
NOTES:
1. All voltages are referenced to ground.
2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VDD is switched off.
3. ICC specified with zero-crossing detection active and operating device serial port in fast mode.
4. ISTBY specified with for VCC equal 3.0V and 5.0V and SDA and SCL are driven to the appropriate
logic levels. ISTBY is specified as the current consumption of the device when SDA and SCL are in the
inactive (high) states.
5. After this period, the first clock pulse is generated.
6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
8. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tRMAX + tSU:DAT = 1000+250=1250 ns before the SCL line is released.
9. CB - total capacitance of one bus line in picofarads, timing referenced to (0.9(VCC) and (0.1)(VCC)).
10. Absolute tolerance is used to determine measured wiper voltage versus expected wiper voltage as
determined by wiper position.
11. Tap-to-tap tolerance is used to determine the change in voltage between successive tap positions. The
DS1807 is specified for a
±0.25 dB tap-to-tap tolerance.
12. Typical values are for tA = 25
°C and nominal supply voltage.
13. Address inputs, A0, A1, and A2, should be tied to either VCC or GND depending on the desired
address selections.
14. These parameters are characterized and not 100% tested.
15. Interchannel matching is used to determine the relative difference in dB between the same position on
each potentiometer. The DS1807 is specified for
±0.5 dB Interchannel matching
16. See Figure 9.
17. Valid at 25
°C only.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1808 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:Dual Log Digital Potentiometer |
| DS1808Z-050 | 功能描述:数字电位计 IC RoHS:否 制造商:Maxim Integrated 电阻:200 Ohms 温度系数:35 PPM / C 容差:25 % POT 数量:Dual 每 POT 分接头:256 弧刷存储器:Volatile 缓冲刷: 数字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作电源电压:1.7 V to 5.5 V 电源电流:27 uA 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:TQFN-16 封装:Reel |
| DS1808Z-050/T&R | 制造商:Maxim Integrated Products 功能描述:DUAL LOG HI VOLTAGE POT T&R - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC POT DUAL LOG HV 50K 16-SOIC |
| DS1808Z-050/T&R | 功能描述:数字电位计 IC RoHS:否 制造商:Maxim Integrated 电阻:200 Ohms 温度系数:35 PPM / C 容差:25 % POT 数量:Dual 每 POT 分接头:256 弧刷存储器:Volatile 缓冲刷: 数字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作电源电压:1.7 V to 5.5 V 电源电流:27 uA 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:TQFN-16 封装:Reel |
| DS1808Z-050+ | 功能描述:数字电位计 IC Dual Log RoHS:否 制造商:Maxim Integrated 电阻:200 Ohms 温度系数:35 PPM / C 容差:25 % POT 数量:Dual 每 POT 分接头:256 弧刷存储器:Volatile 缓冲刷: 数字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作电源电压:1.7 V to 5.5 V 电源电流:27 uA 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:TQFN-16 封装:Reel |
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