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参数资料
| 型号： | DS1851E-010+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/18页 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL NV TEMP CNTRL 8TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 位数： | 8 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 95°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电压，单极 |
| 采样率（每秒）： | * |
DS1851
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Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line can be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data. Figures 3 and 4 detail
how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types
of data transfer are possible.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit.
Within the bus specifications, a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate)
are defined. The DS1851 works in both modes.
Acknowledge: Each receiving device, when addressed, generates an acknowledge after the reception of
each byte. The master device must generate an extra clock pulse that is associated with this acknowledge
bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is a stable low during the high period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end-of-data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line high to enable the master to generate the STOP condition.
1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is
the command/control byte, followed by a number of data bytes. The slave returns an acknowledge bit
after each received byte.
2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the
command/control byte) to the slave. The slave then returns an acknowledge bit. Next, follows a
number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit
after all received bytes other than the last byte. At the end of the last received byte, a ‘not
acknowledge’ can be returned.
The master device generates all serial clock pulses and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated START condition. Since a repeated START condition is
also the beginning of the next serial transfer, the bus will not be released.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1852 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:Optical Transceiver Diagnostic Monitor |
| DS1852B-000 | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| DS1852B-000/C | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| DS1852B-000/T&R | 制造商:Maxim Integrated Products 功能描述:IC MONITOR TXRX OPTICAL 25-BGA |
| DS1852B-000/T&R | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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