参数资料
型号: DS1856B-030+T&R
厂商: Maxim Integrated Products
文件页数: 22/31页
文件大小: 0K
描述: IC RES TEMP-CNTRL 30/10K 16-BGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
接片: 256
电阻(欧姆): 10k,30k
电路数: 2
温度系数: 标准值 50 ppm/°C
存储器类型: 非易失
接口: 2 线串口
电源电压: 2.85 V ~ 5.5 V
工作温度: -40°C ~ 95°C
安装类型: 表面贴装
封装/外壳: 16-LBGA,CSPBGA
供应商设备封装: 16-CSBGA(4x4)
包装: 带卷 (TR)
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
Maxim Integrated
29
DS1856
Stop data transfer: A change in the state of the data
line from low to high while the clock line is high defines
the STOP condition.
Data valid: The state of the data line represents valid
data when, after a START condition, the data line is sta-
ble for the duration of the high period of the clock signal.
The data on the line can be changed during the low peri-
od of the clock signal. There is one clock pulse per bit of
data. Figures 5 and 6 detail how data transfer is accom-
plished on the 2-wire bus. Depending on the state of the
R/W bit, two types of data transfer are possible.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
data bytes transferred between START and STOP con-
ditions is not limited and is determined by the master
device. The information is transferred byte-wise and
each receiver acknowledges with a ninth bit.
STOP
CONDITION
OR REPEATED
START
CONDITION
REPEATED IF MORE BYTES
ARE TRANSFERRED
ACK
START
CONDITION
ACK
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SLAVE ADDRESS
MSB
SCL
SDA
R/W
DIRECTION
BIT
12
6
7
8
9
12
8
9
3–7
Figure 5. 2-Wire Data Transfer Protocol
SDA
SCL
tHD:STA
tLOW
tHIGH
tR
tF
tBUF
tHD:DAT
tSU:DAT
REPEATED
START
tSU:STA
tHD:STA
tSU:STO
tSP
STOP
START
Figure 6. 2-Wire AC Characteristics
相关PDF资料
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