参数资料
型号: DS1856B-030+T&R
厂商: Maxim Integrated Products
文件页数: 8/31页
文件大小: 0K
描述: IC RES TEMP-CNTRL 30/10K 16-BGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
接片: 256
电阻(欧姆): 10k,30k
电路数: 2
温度系数: 标准值 50 ppm/°C
存储器类型: 非易失
接口: 2 线串口
电源电压: 2.85 V ~ 5.5 V
工作温度: -40°C ~ 95°C
安装类型: 表面贴装
封装/外壳: 16-LBGA,CSPBGA
供应商设备封装: 16-CSBGA(4x4)
包装: 带卷 (TR)
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
16
Maxim Integrated
DS1856
TABLE 03 (CONFIGURATION)
Word 0
Word 1
Word 2
Word 3
Row
(hex)
Row
Name
Byte 0/8
Byte 1/9
Byte 2/A
Byte 3/B
Byte 4/C
Byte 5/D
Byte 6/E
Byte 7/F
80
<0>Config0
<8>Mode
<4>Tindex
<4>Res0
<4>Res1
<8>Reserved
88
<8>Config1
Int Enable
Config
Reserved
chip addr
Reserved
Rshift1
Rshift0
90
<8>Scale0
Reserved
Vcc Scale
Mon1 Scale
Mon2 Scale
98
<8>Scale1
Mon3 Scale
Reserved
A0
<8>Offset0
Reserved
Vcc Offset
MON1 Offset
MON2 Offset
A8
<8>Offset1
MON3 Offset
Reserved
Internal Temp Offset*
B0
<9>Pwd Value
PW1 msb
PW1 lsb
PW2 msb
PW2 lsb
EXPANDED BYTES
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Byte
(hex)
Byte
Name
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
80
Mode
Reserved
TEN
AEN
81
Tindex
2
7
2
6
2
5
2
4
2
3
2
1
2
0
82
Res0
2
7
2
6
2
5
2
4
2
3
2
1
2
0
83
Res1
2
7
2
6
2
5
2
4
2
3
2
1
2
0
88
Int Enable
Temp
Vcc
Mon1
Mon2
Mon3
Reserved
89
Config
Reserved
ADEN
ADFIX
Reserved
Inv 1
Inv 2
8C
Chip Addr
2
7
2
6
2
5
2
4
2
3
2
1
2
0
8E
Rshift1
Reserved
Mon1
2
Mon1
1
Mon1
0
Reserved
Mon2
2
Mon2
1
Mon2
0
8F
Rshift0
Reserved
Mon3
2
Mon3
1
Mon3
0
Reserved
92
VCC Scale
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
1
2
0
94
Mon1 Scale
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
1
2
0
96
Mon2 Scale
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
1
2
0
98
Mon3 Scale
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
1
2
0
A2
VCC Offset
SS
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
A4
Mon1 Offset
SS
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
A6
Mon2 Offset
SS
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
A8
Mon3 Offset
SS
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
AE
Temp Offset*
S
2
8
2
7
2
6
2
5
2
4
2
3
2
1
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
B0
PW1 msb
2
31
2
30
2
29
2
28
2
27
2
26
2
25
2
24
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
B2
PW1 lsb
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
1
2
0
B4
PW2 msb
2
31
2
30
2
29
2
28
2
27
2
26
2
25
2
24
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
B6
PW2 lsb
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
1
2
0
*
The final result must be XOR’ed with BB40h.
Memory Map (continued)
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