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| 型号： | DS1869S-C10+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 8/8页 |
| 文件大小： | 0K |
| 描述： | IC RHEOSTAT DALLAST 8SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 产品变化通告： | DS1869 Series Discontinuation 10/May/2012 |
| 标准包装： | 2,000 |
| 系列： | Dallastat™ |
| 接片： | 64 |
| 电阻（欧姆）： | 10k |
| 电路数： | 1 |
| 温度系数： | 标准值 750 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | 上/下 |
| 电源电压： | ± 2.7 V ~ 8 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.209"，5.30mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
| 其它名称： | 90-1869V+C10 |
DS1869
8 of 8
TIMING DIAGRAMS Figure 5
NOTES:
1. All inputs; UC, DC, and D are internally pulled up with a typical resistance of 100 k
.
2. Input logic levels are referenced to -V.
3. ICC is the internal current that flows between -V and +V.
4. Input leakage applies to contact inputs UC and DC and the digital input (D).
5. Wiper current is the maximum current which can flow through the wipers.
6. Capacitance values apply at 25
°C.
7. Input pulse width is the minimum time required for an input to cause an increment or decrement. If
the UC, DC, or D input is held active for longer than 1 second, subsequent increments or decrements
will occur on 100 ms intervals until the inputs UC, DC, and/or D is released to VIH.
8. Repetitive pulsed inputs on UC, DC, or D will be recognized as long as the pulse repetition occurs
within 1 second of each other. Pulses occurring faster than 1 ms apart may not be recognized as
individual inputs but can be interpreted a constant input. Tolerance for pulse timing is
±15% on
minimum inputs.
9. Idle state supply current is measured with no pushbutton pressed and with the wiper RW tied to a
CMOS load.
10. For +V referenced to -V = 5V.
11. Valid at 25
°C only.
tCPW
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