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参数资料
| 型号： | DS1878T+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 21/101页 |
| 文件大小： | 0K |
| 描述： | IC CTLR SFP W/DGTL LDD RX 28TQFN |
| 标准包装： | 2,500 |
| 类型： | SFP+ 控制器 |
| 输入类型： | 模拟，数字 |
| 输出类型： | 数字 |
| 接口： | I²C，LDD，串行 |
| 电流 - 电源： | 2.5mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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DS1878
SFP+ Controller with Digital LDD Interface
26
______________________________________________________________________________________
Figure 17d. TXFOUT When TXD_TXFEN = 0 on Slow Power-On
Die Identification
The DS1878 has an ID hardcoded in its die. Two regis-
ters (Table 02h, Registers CEh–CFh) are assigned for
this feature. The CEh register reads 78h to identify the
part as the DS1878, while the CFh register reads the
current device version.
3-Wire Master for Controlling
the Maxim Laser Driver and
Limiting Amplifier
The device controls a Maxim laser driver and limiting
amplifier over a proprietary 3-wire interface. The device
acts as the master, initiating communication with and
generating the clock for the Maxim slave device(s). It is
a 3-pin interface consisting of SDAOUT (a bidirectional
data line), SCLOUT (clock signal), and a chip-select
output (active high). Two chip selects are provided.
CSEL1OUT is active during all communications.
CSEL2OUT is only active during communications to the
limiting amplifier. By connecting CSEL2OUT to a Maxim
limiting amplifier, there is less noise induced by the
communication interface on the limiting amplifier, since
none of the laser driver communications are processed
by the limiting amplifier.
Protocol
The device initiates a data transfer by asserting the
CSEL_OUT pin. It then starts to generate a clock signal
after CSEL_OUT has been set to 1. Each operation
consists of 16-bit transfers (15-bit address/data, 1-bit
RWN). All data transfers are MSB first.
Write Mode (RWN = 0): The master generates 16 clock
cycles at SCLOUT in total. It outputs 16 bits (MSB first)
to the SDAOUT line at the falling edge of the clock. The
master closes the transmission by setting CSEL_OUT to
0.
Read Mode (RWN = 1): The master generates 16 clock
cycles at SCLOUT in total. It outputs 8 bits (MSB first)
to the SDAOUT line at the falling edge of the clock. The
SDAOUT line is released after the RWN bit has been
transmitted. The slave outputs 8 bits of data (MSB first)
at the rising edge of the clock. The master samples
SDAOUT at the falling edge of SCLOUT. The master
closes the transmission by setting CSEL_OUT to 0.
BIT
NAME
DESCRIPTION
15:9
Address
7-bit internal register address
8
RWN
0: write; 1: read
7:0
Data
8-bit read or write data
VPOA
VCC
TXD OR
SOFT TXD*
TXFOUT (1)
TXFOUT (2)
CONDITION 1: VCCTXF = 0, VCC LO ALARM OR WARNING FLAG ENABLED TO CREATE TXFOUT.
CONDITION 2: VCCTXF = 1 and (VCC LO ALARM OR WARNING FLAG IS ENABLED).
*DON'T CARE ABOUT TXD STATE.
VCC-LO
13ms
< tRR
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