参数资料
型号: DS1884AT+T
厂商: Maxim Integrated Products
文件页数: 52/92页
文件大小: 0K
描述: IC SFP PON ONU CTRLR 24TQFN
标准包装: 2,500
系列: *
DS1884
SFP and PON ONU Controller
with Digital LDD Interface
56
Maxim Integrated
A2h Table 01h, Register F8h: ALARM EN3 OR EE
POWER-ON VALUE
00h
READ ACCESS
PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS
PW2 or (PW1 and RWTBL1C)
MEMORY TYPE
Nonvolatile (SEE)
F8h
TEMP HI
TEMP LO
VCC HI
VCC LO
TXB HI
TXB LO
TXP HI
TXP LO
BIT 7
BIT 0
Layout is identical to ALARM3 in Lower Memory, Register 70h. Enables alarms to create TXFINT (Lower Memory,
Register 71h) logic. The MASK bit (A2h Table 02h, Register 89h) determines whether this memory exists in A2h
Table 01h or 05h. When in A2h Table 05h, this location at A2h Table 01h becomes EE.
BIT 7
TEMP HI:
0 = Disables interrupt from TEMP HI alarm.
1 = Enables interrupt from TEMP HI alarm.
BIT 6
TEMP LO:
0 = Disables interrupt from TEMP LO alarm.
1 = Enables interrupt from TEMP LO alarm.
BIT 5
VCC HI:
0 = Disables interrupt from VCC HI alarm.
1 = Enables interrupt from VCC HI alarm.
BIT 4
VCC LO:
0 = Disables interrupt from VCC LO alarm.
1 = Enables interrupt from VCC LO alarm.
BIT 3
TXB HI:
0 = Disables interrupt from TXB HI alarm.
1 = Enables interrupt from TXB HI alarm.
BIT 2
TXB LO:
0 = Disables interrupt from TXB LO alarm.
1 = Enables interrupt from TXB LO alarm.
BIT 1
TXP HI:
0 = Disables interrupt from TXP HI alarm.
1 = Enables interrupt from TXP HI alarm.
BIT 0
TXP LO:
0 = Disables interrupt from TXP LO alarm.
1 = Enables interrupt from TXP LO alarm.
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