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| 型号： | DS1884T+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 21/92页 |
| 文件大小： | 0K |
| 描述： | IC SFP PON ONU CTRLR 24TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 产品变化通告： | DS1884 Series Discontinuation 03/Aug/2012 |
| 标准包装： | 2,500 |
| 系列： | * |
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DS1884
SFP and PON ONU Controller
with Digital LDD Interface
28
Maxim Integrated
DS1884 Master Communication
Interface
The DS1884 controls the MAX3710 using a proprietary
3-wire interface. The DS1884 configures the MAX3710 on
startup and then continuously updates the MAX3710 with
new LUT values. The DS1884 operates in one of three
modes: open loop, APC loop, and dual closed loop. The
DS1884 can also configure the MAX3945 on startup. The
communication between the DS1884 and the MAX3710
and MAX3945 is transparent to the end user. In addition,
commands can be issued to the MAX3710 and MAX3945
using the DS1884’s manual mode.
3-Wire Master Interface
The DS1884 acts as the master, initiating communica-
tion with and generating the clock for the Maxim slave
device(s). It is a 3-pin interface consisting of SDAOUT,
a bidirectional data line; clock signal SCLOUT; and
CSEL1OUT chip-select output (active high). A second,
independent chip select (CSEL2OUT) is provided for use
with the MAX3945.
Protocol
The DS1884 initiates a data transfer by asserting the
CSEL1OUT or CSEL2OUT pin. It then starts to generate
a clock signal after CSEL1OUT or CSEL2OUT has been
set to 1. Each operation consists of 16 bit transfers (15-bit
address/data, 1-bit RWN). All data transfers are MSB first.
Write Mode (RWN = 0): The master generates 16 clock
cycles at SCLOUT in total. It outputs 16 bits (MSB first)
to the SDAOUT line at the falling edge of the clock. The
master closes the transmission by setting CSEL1OUT
and CSEL2OUT to 0.
Read Mode (RWN = 1): The master generates 16 clock
cycles at SCLOUT in total. It outputs 8 bits (MSB first)
to the SDAOUT line at the falling edge of the clock. The
SDAOUT line is released after the RWN bit has been
transmitted. The slave outputs 8 bits of data (MSB first) at
rising edge of the clock. The master samples SDAOUT at
the falling edge of SCLOUT. The master closes the trans-
mission by setting the CSEL1OUT and CSEL2OUT to 0.
Table 5. 3-Wire Transaction Detail
Figure 13. 3-Wire Interface Timing Diagram
BIT
NAME
DESCRIPTION
15:9
Address
7-bit internal register address
8
RWN
0: write, 1: read
7:0
Data
8-bit read or write data
CSEL_OUT
SCLOUT
SDAOUT
CSEL_OUT
NOTE: SEE THE 3-WIRE DIGITAL INTERFACE SPECIFICATION TABLE FOR DETAILS. CSEL_OUT IMPLIES CSEL1OUT OR CSEL2OUT.
SCLOUT
SDAOUT
12
3
456
78
A6
9101112131415
0
12
3
456
789
10
11
12
13
14
15
0
A5
A4
A3
A2
A1
RWN
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
RWN
WRITE MODE
READ MODE
A0
A6
A5
A4
A3
A2
A1
A0
tL
tCH tCL
tL
tDS
tDH
tDS
tRS
tDH
tT
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| DS1886T+T | 功能描述:接口 - 专用 PON ONU/SFP CTRLR W/DIG LDD INT RoHS:否 制造商:Texas Instruments 产品类型:1080p60 Image Sensor Receiver 工作电源电压:1.8 V 电源电流:89 mA 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:BGA-59 |
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