参数资料
型号: DS1884T+T
厂商: Maxim Integrated Products
文件页数: 29/92页
文件大小: 0K
描述: IC SFP PON ONU CTRLR 24TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
产品变化通告: DS1884 Series Discontinuation 03/Aug/2012
标准包装: 2,500
系列: *
DS1884
SFP and PON ONU Controller
with Digital LDD Interface
35
Maxim Integrated
Acknowledgement (ACK and NACK): An acknowl-
edgement (ACK) or not-acknowledge (NACK) is
always the 9th bit transmitted during a byte trans-
fer. The device receiving data (the master during a
read or the slave during a write operation) performs
an ACK by transmitting a zero during the 9th bit.
A device performs a NACK by transmitting a one
during the 9th bit. Timing for the ACK and NACK is
identical to all other bit writes (Figure 18). An ACK
is the acknowledgment that the device is properly
receiving data. A NACK is used to terminate a read
sequence or as an indication that the device is not
receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgement from
the slave to the master. The 8 bits transmitted by the
master are done according to the bit write definition
and the acknowledgement is read using the bit read
definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition, and the master transmits an ACK using
the bit write definition to receive additional data bytes.
The master must NACK the last byte read to terminate
communication so the slave returns control of SDA to
the master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
The DS1884 responds to two slave addresses. The
auxiliary memory always responds to a fixed I2C
slave address, A0h. The Lower Memory and Tables
00h–08h respond to I2C slave addresses that can be
configured to any value between 00h–FEh using the
DEVICE ADDRESS byte (A2h Table 02h, Register 8Ch).
The user also must set the ASEL bit (A2h Table 02h,
Register 89h) for this address to be active. By writing
the correct slave address with R/W = 0, the master indi-
cates that it would write data to the slave. If R/W = 1, the
master reads data from the slave. If an incorrect slave
address is written, the device assumes the master is
communicating with another I2C device and ignores
the communications until the next START condition is
sent. If the main device’s slave address is programmed
to be A0h, access to the auxiliary memory is disabled.
Memory Address: During an I2C write operation to the
device, the master must transmit a memory address to
identify the memory location where the slave is to store
the data. The memory address is always the second
byte transmitted during a write operation following the
slave address byte.
Figure 18. I2C Timing Diagram
SCL
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
SDA
STOP
START
REPEATED
START
tBUF
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHD:STA
tSP
tSU:STA
tHIGH
tR
tF
tLOW
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