参数资料
型号: DS18S20-PAR+T&R
厂商: Maxim Integrated
文件页数: 7/20页
文件大小: 0K
描述: IC THERM MICROLAN HI-PREC TO-92
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
感应温度: -55°C ~ 125°C
输出类型: 数字
电源电压: 3 V ~ 5.5 V
精确度: ±0.5°C
封装/外壳: TO-226-3、TO-92-3(TO-226AA)成形引线
供应商设备封装: TO-92-3
包装: 带卷 (TR)
DS18S20-PAR
1-WIRE BUS SYSTEM
The 1-Wire bus system uses a single bus master to control one or more slave devices. The DS18S20-
PAR is always a slave. When there is only one slave on the bus, the system is referred to as a “single-
drop” system; the system is “multi-drop” if there are multiple slaves on the bus. All data and commands
are transmitted least significant bit first over the 1-Wire bus.
The following discussion of the 1-Wire bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-Wire signaling (signal types and timing).
HARDWARE CONFIGURATION
The 1-Wire bus has by definition only a single data line. Each device (master or slave) interfaces to the
data line via an open drain or 3–state port. This allows each device to “release” the data line when the
device is not transmitting data so the bus is available for use by another device. The 1-Wire port of the
DS18S20-PAR (the DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 8.
The 1-Wire bus requires an external pullup resistor of approximately 5 k W ; thus, the idle state for the 1-
Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle
state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wire
bus is in the inactive (high) state during the recovery period. If the bus is held low for more than 480 m s,
all components on the bus will be reset. In addition, to assure that the DS18S20-PAR has sufficient
supply current during temperature conversions, it is necessary to provide a strong pullup (such as a
MOSFET) on the 1-Wire bus whenever temperature conversions or EEPROM writes are taking place (as
described in the PARASITE POWER section).
HARDWARE CONFIGURATION Figure 8
V PU
Micro-
processor
R X
Strong
Pullup
V PU
4.7K
1-wire bus
DQ
Pin
DS18S20-PAR 1-WIRE PORT
R X
5 μA
T X
R X = RECEIVE
T X = TRANSMIT
Typ.
T X
100 W
MOSFET
TRANSACTION SEQUENCE
The transaction sequence for accessing the DS18S20-PAR is as follows:
Step 1. Initialization
Step 2. ROM Command (followed by any required data exchange)
Step 3. DS18S20-PAR Function Command (followed by any required data exchange)
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