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参数资料
| 型号： | DS18S20Z+T&R |
| 厂商： | Maxim Integrated |
| 文件页数： | 14/23页 |
| 文件大小： | 0K |
| 描述： | IC THERM MICROLAN HI-PREC 8-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 感应温度： | -55°C ~ 125°C |
| 输出类型： | 数字 |
| 电源电压： | 3 V ~ 5.5 V |
| 精确度： | ±0.5°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
DS18S20
READ-TIME SLOTS
The DS18S20 can only transmit data to the master when the master issues read-time slots. Therefore, the
master must generate read-time slots immediately after issuing a Read Scratchpad [BEh] or Read Power
Supply [B4h] command, so that the DS18S20 can provide the requested data. In addition, the master can
generate read-time slots after issuing Convert T [44h] or Recall E 2 [B8h] commands to find out the status
of the operation as explained in the DS18S20 Function Commands section.
All read-time slots must be a minimum of 60 μ s in duration with a minimum of a 1 μ s recovery time
between slots. A read-time slot is initiated by the master device pulling the 1-Wire bus low for a
minimum of 1 μ s and then releasing the bus (see Figure 11). After the master initiates the read-time slot,
the DS18S20 will begin transmitting a 1 or 0 on bus. The DS18S20 transmits a 1 by leaving the bus high
and transmits a 0 by pulling the bus low. When transmitting a 0, the DS18S20 will release the bus by the
end of the time slot, and the bus will be pulled back to its high idle state by the pullup resister. Output
data from the DS18S20 is valid for 15 μ s after the falling edge that initiated the read-time slot. Therefore,
the master must release the bus and then sample the bus state within 15 μ s from the start of the slot.
Figure 12 illustrates that the sum of T INIT , T RC , and T SAMPLE must be less than 15 μ s for a read-time slot.
Figure 13 shows that system timing margin is maximized by keeping T INIT and T RC as short as possible
and by locating the master sample time during read-time slots towards the end of the 15 μ s period.
Figure 11. Read/Write Time Slot Timing Diagram
START
OF SLOT
START
OF SLOT
V PU
1-WIRE BUS
GND
MASTER WRITE “0” SLOT
60 μ s < T X “0” < 120 μ s
MASTER WRITE “1” SLOT
1 μ s < T REC < ∞
> 1 μ s
MIN
DS18S20 Samples
TYP
MAX
MIN
DS18S20 Samples
TYP
MAX
15 μ s
15 μ s
30 μ s
15 μ s
15 μ s
30 μ s
V PU
1-WIRE BUS
GND
MASTER READ “0” SLOT
MASTER READ “1” SLOT
1 μ s < T REC < ∞
> 1 μ s
15 μ s
Master samples
45 μ s
> 1 μ s
15 μ s
Master samples
LINE TYPE LEGEND
Bus master pulling low
Resistor pullup
14 of 23
DS18S20 pulling low
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