参数资料
型号: DS1992L-F5+
厂商: Maxim Integrated
文件页数: 13/17页
文件大小: 0K
描述: IBUTTON MEMORY 1KBit F5
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
RoHS指令信息: IButton RoHS Compliance Plan
标准包装: 25
系列: iButton®
存储容量: 128B
存储器类型: NVRAM
产品目录页面: 1431 (CN2011-ZH PDF)
DS1992/DS1993
Figure 10. INITIALIZATION PROCEDURE RESET AND PRESENCE PULSE
V PULLUP
V PULLUP MIN
V IH MIN
V IL MAX
0V
MASTER TX
"RESET PULSE"
MASTER RX "PRESENCE PULSE"
t RSTH
t RSTL
t R
t PDH
t PDL
RESISTOR
MASTER
DS199x
480 μs ≤ t RSTL < ∞ *
480 μs ≤ t RSTH < ∞ **
15 μs ≤ t PDH < 60 μs
60 ≤ t PDL < 240 μs
* In order not to mask interrup signaling
by other devices on the 10Wire bus t RSTL
+ t R should always be less than 960 us
** Includes recovery time
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 11. The master driving the data line
low initiates all time slots. The falling edge of the data line synchronizes the DS199x to the master by
triggering a delay circuit in the DS199x. During write time slots, the delay circuit determines when the
DS199x samples the data line. For a read data time slot, if a 0 is to be transmitted, the delay circuit
determines how long the DS199x holds the data line low overriding the 1 generated by the master. If the
data bit is a 1, the iButton leaves the read data time slot unchanged.
Figure 11. READ/WRITE TIMING DIAGRAM
Write-One Time Slot
V PULLUP
t SLOT
t REC
V PULLUP MIN
V IH MIN
DS199x
Sampling Window
V IL MAX
0V
t LOW1
15μs
60μs
1 μs ≤ t < 15 μs
RESISTOR
MASTER
60 μs ≤ t SLOT < 120 μs
LOW1
1 μs ≤ t REC < ∞
13 of 17
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DS1992LP 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog IC
DS1992LR 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog IC
DS1992P 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog IC