参数资料
型号: DS21348TN
厂商: DALLAS SEMICONDUCTOR
元件分类: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, PQFP44
封装: TQFP-44
文件页数: 16/67页
文件大小: 339K
代理商: DS21348TN
DS21348/Q348
23 of 67
6. CONTROL REGISTERS
CCR1 (00H): COMMON CONTROL REGISTER 1
(MSB)
(LSB)
ETS
NRZE
RCLA
ECUE
JAMUX
TTOJ
TTOR
LOTCMC
SYMBOL
POSITION
NAME AND DESCRIPTION
ETS
CCR1.7
E1/T1 Select.
0 = E1
1 = T1
NRZE
CCR1.6
NRZ Enable.
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a
positive going pulse when device receives a BPV, CV, or EXZ.
RCLA
CCR1.5
Receive Carrier Loss Alternate Criteria.
0 = RCL declared upon 255 (E1) or 192 (T1) consecutive zeros
1 = RCL declared upon 2048 (E1) or 1544 (T1) consecutive
zeros
ECUE
CCR1.4
Error Counter Update Enable. A 0 to 1-transition forces the
next clock cycle to load the error counter registers with the
latest counts and reset the counters. The user must wait a
minimum of two clocks cycles (976ns for E1 and 1296ns for
T1) before reading the error count registers to allow for a proper
update. See Section 6 for details.
JAMUX
CCR1.3
Jitter Attenuator MUX. Controls the source for JACLK. See
Figure 3-1.
0 = JACLK sourced from MCLK (2.048 MHz or 1.544 MHz at
MCLK)
1 = JACLK sourced from internal PLL (2.048 MHz at MCLK)
TTOJ
CCR1.2
TCLK to JACLK. Internally connects TCLK to JACLK. See
Figure 3-3.
0 = disabled
1 = enabled
TTOR
CCR1.1
TCLK to RCLK. Internally connects TCLK to RCLK. See
Figure 3-3
0 = disabled
1 = enabled
LOTCMC
CCR1.0
Loss Of Transmit Clock Mux Control. Determines whether
the transmit logic should switch to JACLK if the TCLK input
should fail to transition. See Figure 3-3.
0 = do not switch to JACLK if TCLK stops
1 = switch to JACLK if TCLK stops
相关PDF资料
PDF描述
DS21348G DATACOM, PCM TRANSCEIVER, BGA49
DS21Q348N DATACOM, PCM TRANSCEIVER, PBGA144
DS21Q348 DATACOM, PCM TRANSCEIVER, PBGA144
DS21352L DATACOM, PCM TRANSCEIVER, PQFP100
DS21352LN DATACOM, PCM TRANSCEIVER, PQFP100
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