参数资料
型号: DS21348TN
厂商: DALLAS SEMICONDUCTOR
元件分类: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, PQFP44
封装: TQFP-44
文件页数: 4/67页
文件大小: 339K
代理商: DS21348TN
DS21348/Q348
12 of 67
Acronym
Pin
I/O
Description
JAMUX
9I
Jitter Attenuator MUX. Controls the source for JACLK. See
Figure 3-1and Table 4-9.
0 = JACLK sourced from MCLK (2.048 MHz or 1.544 MHz at
MCLK)
1 = JACLK sourced from internal PLL (2.048 MHz at MCLK)
JAS
10
I
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
L0/L1/L2
7/
6/
5
I
Transmit LIU Waveshape Select Bits 0 & 1 [H/W Mode]. These
inputs determine the waveshape of the transmitter. See Table 9-1 &
Table 9-2.
LOOP0/
LOOP1
16/
17
I
Loopback Select Bits 0 & 1 [H/W Mode]. These inputs determine
the active loopback mode (if any). See Table 4-4.
MCLK
30
I
Master Clock. A 2.048 MHz (+/-50 ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544
MHz clock source is optional.
See note 2 on clock accuracy at the end of this table.
MM0/
MM1
18/
19
I
Monitor Mode Select Bits 0 & 1 [H/W Mode]. These inputs
determine if the receive equalizer is in a monitor mode. See Table
4-7.
NA
-I
Not Assigned. Should be tied low.
NRZE
3I
NRZ Enable [H/W Mode].
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a
positive going pulse when device receives a BPV, CV, or EXZ.
OCES
9I
Output Clock Edge Select. Selects whether the serial port data
output (SDO) is valid on the rising (OCES = 1) or falling edge
(OCES = 0) of SCLK.
PBEO
24
O
PRBS Bit Error Output. The receiver will constantly search for a
2
15-1 or a 220-1 PRBS depending on the ETS bit setting (CCR1.7).
Remains high if out of synchronization with the PRBS pattern.
Goes low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and
ECR2 registers by setting CCR6.2 to a logic 1.
PBTS
44
I
Parallel Bus Type Select. When using the parallel port (BIS1 = 0),
set high to select Motorola bus timing, set low to select Intel bus
timing. This pin controls the function of the RD*(DS*), ALE(AS),
and WR*(R/W*) pins. If PBTS = 1 and BIS1 = 0, then these pins
assume the Motorola function listed in parenthesis (). In serial port
mode, this pin should be tied low.
RCLK
40
O
Receive Clock. Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
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