参数资料
型号: DS21354LN
厂商: Maxim Integrated Products
文件页数: 96/124页
文件大小: 0K
描述: IC TXRX E1 1-CHIP 3.3V 100-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
产品变化通告: Product Discontinuation 20/Feb/2012
标准包装: 90
功能: 单芯片收发器
接口: E1,HDLC
电路数: 1
电源电压: 3.14 V ~ 3.47 V
电流 - 电源: 75mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 托盘
包括: 远程和 AIS 警报检测器 / 发生器
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
73 of 124
14.4.
HDLC Register Description
HCR: HDLC CONTROL REGISTER (Address = B0 Hex)
(MSB)
(LSB)
RHR
TFS
THR
TABT
TEOM
TZSD
TCRCD
SYMBOL
POSITION
NAME AND DESCRIPTION
HCR.7
Not Assigned. Should be set to zero when written.
RHR
HCR.6
Receive HDLC Reset. A 0-to-1 transition will reset the HDLC controller.
Must be cleared and set again for a subsequent reset.
TFS
HCR.5
Transmit Flag/Idle Select.
0 = 7Eh
1 = FFh
THR
HCR.4
Transmit HDLC Reset. A 0-to-1 transition will reset the HDLC
controller. Must be cleared and set again for a subsequent reset.
TABT
HCR.3
Transmit Abort. A 0-to-1 transition will cause the FIFO contents to be
dumped and one FEh abort to be sent followed by 7Eh or FFh flags/idle
until a new packet is initiated by writing new data into the FIFO. Must be
cleared and set again for a subsequent abort to be sent.
TEOM
HCR.2
Transmit End of Message. Should be set to a one just before the last data
byte of a HDLC packet is written into the transmit FIFO at THFR. This bit
will be cleared by the HDLC controller when the last byte has been
transmitted.
TZSD
HCR.1
Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
TCRCD
HCR.0
Transmit CRC Defeat.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
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