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| 型号： | DS21372T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 17/22页 |
| 文件大小： | 0K |
| 描述： | IC TESTER BIT ERROR 3.3V 32-TQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS |
| 产品变化通告： | Product Discontinuation 20/Feb/2012 |
| 标准包装： | 250 |
| 功能： | 位误码率测试器（BERT） |
| 接口： | T1 |
| 电路数： | 1 |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 10mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-TQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
| 包括： | 错误计数器，样式发生器和检测器 |
DS21372
4 of 22
DETAILED PIN DESCRIPTION Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
1TL
I
Transmit Load. A positive-going edge loads the pattern generator with
the contents of the Pattern Set Registers. The MSB of the repetitive or
pseudorandom pattern appears at TDATA after the third positive edge of
TCLK from asserting TL. TL is logically OR’ed with PCR.7 and should
be tied to VSS if not used. See Figure 8 for timing information.
2
AD0
I/O
Data Bus. An 8-bit multiplexed address/data bus.
3
AD1
I/O
Data Bus. An 8-bit multiplexed address/data bus.
4
TEST
I
Test. Set high to 3-state all output pins ( INT , ADx, TDATA, RLOS).
Should be tied to VSS to enable all outputs.
5VSS
-
Signal Ground. 0.0V. Should be tied to local ground plane.
6
AD2
I/O
Data Bus. An 8-bit multiplexed address/data bus.
7
AD3
I/O
Data Bus. An 8-bit multiplexed address/data bus.
8
AD4
I/O
Data Bus. An 8-bit multiplexed address/data bus.
9
AD5
I/O
Data Bus. An 8-bit multiplexed address/data bus.
10
AD6
I/O
Data Bus. An 8-bit multiplexed address/data bus.
11
AD7
I/O
Data Bus. An 8-bit multiplexed address/data bus.
12
VSS
-
Signal Ground. 0.0V. Should be tied to local ground plane.
13
VDD
-
Positive Supply. 3.3V.
14
BTS
I
Bus Type Select. Strap high to select Motorola bus timing; strap low to
select Intel bus timing. This pin controls the function of the RD (DS),
ALE(AS), and WR (R/ W ) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().
15
RD
(DS)
I
Read Input (Data Strobe).
16
CS
I
Chip Select. Must be low to read or write the port.
17
ALE(AS)
I
Address Latch Enable (Address Strobe). A positive going edge serves
to demultiplex the bus.
18
WR
(R/ W )
I
Write Input (Read/Write).
19
INT
O
Alarm Interrupt. Flags host controller during conditions defined in
Status Register. Active low, open drain output.
20
VDD
-
Positive Supply. 3.3V.
21
VSS
-
Signal Ground. 0.0V. Should be tied to local ground plane.
22
LC
I
Load Count. A positive-going edge latches the current bit and bit error
count into the user accessible BCR and BECR registers and clears the
internal count registers. LC is logically OR’ed with control bit PCR.4.
Should be tied to VSS if not used.
23
RLOS
O
Receive Loss Of Sync. Indicates the real time status of the receive
synchronizer. Active high output.
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