参数资料
型号: DS2141A
厂商: DALLAS SEMICONDUCTOR
元件分类: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PDIP40
封装: 0.600 INCH, DIP-40
文件页数: 26/39页
文件大小: 470K
代理商: DS2141A
DS2141A
32 of 39
TRANSMIT SIDE BOUNDARY TIMING (WITH ELASTIC STORE(S) DISABLED)
NOTES:
1. There is a 10 TCLK delay from TSER to TPOS, TNEG.
2. TSYNC is in the input mode (TCR2.2=0).
3. TSYNC is in the output mode (TCR2.2=1).
4. TCHBLK is programmed to block Channel 1.
LINE INTERFACE CONTROL TIMING
NOTES:
1. A write to CRB1 will cause the DS2141A to output this sequence.
2. A write to CRB2 will cause the DS2141A to output this sequence.
3. Timing numbers are based on RCLK=1.544 MHz with 50% duty cycle.
相关PDF资料
PDF描述
DS2143N DATACOM, FRAMER, PDIP40
DS2143QN DATACOM, FRAMER, PQCC44
DS2143Q DATACOM, FRAMER, PQCC44
DS2143 DATACOM, FRAMER, PDIP40
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