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参数资料
| 型号： | DS2143 |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PDIP40 |
| 封装： | 0.600 INCH, DIP-40 |
| 文件页数： | 6/44页 |
| 文件大小： | 552K |
| 代理商： | DS2143 |
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DS2143/DS2143Q
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4.0 STATUS AND INFORMATION REGISTERS
There is a set of four registers that contain information on the current real time status of the DS2143:
Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer
Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one
of these three registers will be set to a 1. All of the bits in these registers operate in a latched fashion
(except for the SSR). This means that if an event occurs and a bit is set to a 1 in any of the registers, it
will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set
again until the event has occurred again or if the alarm(s) is still present.
The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to
the register will inform the DS2143 which bits the user wishes to read and have cleared. The user will
write a byte to one of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in
the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit
location, the read register will be updated with current value and it will be cleared. When a 0 is written to
a bit position, the read register will not be updated and the previous value will be held. A write to the
status and information registers will be immediately followed by a read of the same register. The read
result should be logically AND’ed with the mask byte that was just written and this value should be
written back into the same register to insure that the bit does indeed clear. This second write is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. This scheme allows an external microcontroller or microprocessor to individually poll
certain bits without disturbing the other bits in the register. This operation is key in controlling the
DS2143 with higher order software languages.
The SSR register operates differently than the other three. It is a read only register and it reports the status
of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of
this register with a write.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1 and INT2
pins respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked
from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2)
respectively.
相关PDF资料 |
PDF描述 |
|---|---|
| DS2148GN | DATACOM, PCM TRANSCEIVER, BGA49 |
| DS2148G | DATACOM, PCM TRANSCEIVER, BGA49 |
| DS2148TN | DATACOM, PCM TRANSCEIVER, PQFP44 |
| DS2148T | DATACOM, PCM TRANSCEIVER, PQFP44 |
| DS2151QNB | DATACOM, FRAMER, PQCC44 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2143N | 功能描述:网络控制器与处理器 IC E1 Controller w/Elastic Store RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2143Q | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2143Q/T&R | 制造商:Maxim Integrated Products 功能描述:IC CONTROLLER E1 5V LP 44-PLCC 制造商:Maxim Integrated Products 功能描述:Network Controller & Processor ICs E1 Controller w/Elastic Store |
| DS2143Q/T&R | 功能描述:网络控制器与处理器 IC E1 Controller w/Elastic Store RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2143Q+ | 功能描述:网络控制器与处理器 IC E1 Controller w/Elastic Store RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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