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参数资料
| 型号： | DS2151QB |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PQCC44 |
| 封装： | 0.652 INCH, PLASTIC, LCC-44 |
| 文件页数： | 7/62页 |
| 文件大小： | 921K |
| 代理商： | DS2151QB |
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DS2151Q
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4.1 Local Loopback
When CCR1.6 is set to a 1, the DS2151Q will be forced into Local Loopback (LLB). In this loopback,
data will continue to be transmitted as normal through the transmit side of the SCT. Data being received
at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass
through the jitter attenuator and the jitter attenuator should be programmed to be in the transmit path.
LLB is primarily used in debug and test applications. See Figure 1-1 for more details.
4.2 Remote Loopback
When CCR1.4 is set to a 1, the DS2151Q will be forced into Remote Loopback (RLB). In this loopback,
data recovered off the T1 line from the RTIP and RRING pins will be transmitted back onto the T1 line
(with any BPVs that might have occurred intact) via the TTIP and TRING pins. Data will continue to
pass through the receive side of the DS2151Q as it would normally and the data at the TSER input will be
ignored. Data in this loopback will pass through the jitter attenuator. RLB is used to place the DS2151Q
into “line” loopback, which is a requirement of both ANSI T1.403 and AT&T TR62411. See Figure 1-1
for more details.
4.3 Payload Loopback
When CCR1.1 is set to a 1, the DS2151Q will be forced into Payload Loopback (PLB). Normally, this
loopback is only enabled when ESF framing is being performed. In a PLB situation, the DS2151Q will
loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit
section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are
reinserted by the DS2151Q. When PLB is enabled, the following will occur:
1) Data will be transmitted from the TTIP and TRING pins synchronous with RCLK instead of
TCLK.
2) All the receive side signals will continue to operate normally.
3) The TCHCLK and TCHBLK signals are forced low.
4) Data at the TSER pin is ignored.
5) The TLCLK signal will become synchronous with RCLK instead of TCLK.
4.4 Framer Loopback
When CCR1.0 is set to a 1, the DS2151Q will enter a Framer Loopback (FLB) mode. This loopback is
useful in testing and debugging applications. In FLB, the DS2151Q will loop data from the transmit side
back to the receive side. When FLB is enabled, the following will occur:
1) Unless the RLB is active, an unframed all 1s code will be transmitted at TTIP and TRING.
2) Data off the T1 line at RTIP and RRING will be ignored.
3) The RCLK output will be replaced with the TCLK input.
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PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2151QB/T&R | 制造商:Maxim Integrated Products 功能描述:T1 SINGLE CHIP XCVR REV B T&R - Tape and Reel |
| DS2151QB/T&R+ | 制造商:Maxim Integrated Products 功能描述:FRAMER DS1/E1/ISDN-PRI/T1 5V 44PLCC - Tape and Reel |
| DS2151QB/T&R | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2151QB+ | 功能描述:网络控制器与处理器 IC T1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2151QB+T&R | 制造商:Maxim Integrated Products 功能描述:FRAMER DS1/E1/ISDN-PRI/T1 5V 44PLCC - Tape and Reel |
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