参数资料
型号: DS2154LN+
厂商: Maxim Integrated Products
文件页数: 35/87页
文件大小: 0K
描述: IC TXRX E1 1CHIP 5V ENH 100-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 90
类型: 收发器
驱动器/接收器数: 1/1
规程: E1
电源电压: 4.75 V ~ 5.25 V
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 管件
DS2154
40 of 87
6.2 CRC4 Error Counter
CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant
word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the
maximum CRC4 count in a 1-second period is 1000, this counter cannot saturate. The counter is disabled
during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync
occurs at the CAS level.
CRCCR1: CRC4 COUNT REGISTER 1 (Address = 02 Hex)
CRCCR2: CRC4 COUNT REGISTER 2 (Address = 03 Hex)
(MSB)
(LSB)
(Note 1)
CRC9
CRC8
CRCCR1
CRC7
CRC6
CRC5
CRC4
CRC3
CRC2
CRC1
CRC0
CRCCR2
SYMBOL
POSITION
NAME AND DESCRIPTION
CRC9
CRCCR1.1
MSB of the 10-bit CRC4 error count.
CRC0
CRCCR2.0
LSB of the 10-bit CRC4 error count.
Note 1: The upper 6 bits of CRCCR1 at address 02 are the most significant bits of the 12-bit FAS error counter.
6.3 E-Bit Counter
E-bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of
a 10-bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15
on E1 lines running with CRC4 multiframe. These count registers will increment once each time the
received E-bit is set to 0. Since the maximum E-bit count in a 1-second period is 1000, this counter
cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will
continue to count if loss of multiframe sync occurs at the CAS level.
EBCR1: E-BIT COUNT REGISTER 1 (Address = 04 Hex)
EBCR2: E-BIT COUNT REGISTER 2 (Address = 05 Hex)
(MSB)
(LSB)
(Note 1)
EB9
EB8
EBCR1
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
EBCR2
SYMBOL
POSITION
NAME AND DESCRIPTION
EB9
EBCR1.1
MSB of the 10-bit E-Bit count.
EB0
EBCR2.0
LSB of the 10-bit E-Bit count.
Note 1: The upper 6 bits of EBCR1 at address 04 are the least significant bits of the 12-bit FAS error counter.
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