参数资料
型号: DS2165Q
厂商: DALLAS SEMICONDUCTOR
元件分类: Codec
英文描述: A/MU-LAW, ADPCM CODEC, PQCC28
封装: PLASTIC, LCC-28
文件页数: 11/18页
文件大小: 313K
代理商: DS2165Q
DS2165/DS2165Q
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OVERVIEW
The DS2165 contains three major functional blocks: a high performance (10 MIPS) DSP engine, two
independent PCM interfaces (X and Y) which connect directly to serial Time Division Multiplexed
(TDM) backplanes, and a serial port that can configure the device on-the-fly via an external controller. A
10 MHz master clock is required by the DSP engine. The DS2165 can be configured to perform either
two expansions, two compressions, or one expansion and one compression. The PCM/ADPCM data
interfaces support data rates from 256 kHz to 4.096 MHz. Typically, the PCM data rates will be 1.544
MHz for
-law and 2.048 MHz for A-law. Each channel on the device samples the serial input PCM or
ADPCM bit stream during a user-programmed input time slot, processes the data and outputs the result
during a user-programmed output time slot.
Each PCM interface has a control register which specifies functional characteristics (compress, expand,
bypass, and idle), data format (
-law or A-law), and algorithm reset control. With the SPS pin strapped
high, the software mode is enabled and the serial port can be used to configure the device. In this mode, a
novel addressing scheme allows multiple devices to share a common 3-wire control bus, simplifying
system-level interconnect.
With SPS low, the hardware mode is enabled. This mode disables the serial port and maps certain control
register bits to some of the address and serial port pins. Under the hardware mode, no external host
controller is required and all PCM/ADPCM input and output time slots default to time slot 0.
HARDWARE RESET
RST
allows the user to reset both channel algorithms and the contents of the internal registers. This pin
must be held low for at least 1 ms on system power-up after the master clock is stable to ensure that that
the device has initialized properly. RST should also be asserted when changing to or from the hardware
mode. RST clears all bits of the Control Register for both channels except the IPD bits; the IPD bits for
both channels are set to 1.
SOFTWARE MODE
Tying SPS high enables the software mode. In this mode, an external host controller writes configuration
data to the DS2165 via the serial port through inputs SCLK, SDI, and CS . (See Figure 2.) Each write to
the DS2165 is either a 2-byte write or a 4-byte write. A 2-byte write consists of the Address/Command
Byte (ACB), followed by a byte to configure the Control Register (CR) for either the X or Y channel. The
4-byte write consists of the ACB, followed by a byte to configure the CR, and then 1 byte to set the input
time slot and another byte to set the output time slot.
ADDRESS/COMMAND BYTE
In the software mode, the address/command byte is the first byte written to the serial port; it identifies
which of the 64 possible ADPCM processors sharing the port wiring is to be updated. Address data must
match that at inputs A0 to A5. If no match occurs, the device ignores the following configuration data. If
an address match occurs, the next 3 bytes written are accepted as control, input and output time slot data.
Bit ACB.6 determines which side (X or Y) of the device is to be updated. The PCM and ADPCM
outputs are tristated during register updates.
CONTROL REGISTER
The control register establishes idle, algorithm reset, bypass, data format and channel coding for the
selected channel.
The X and Y side PCM interfaces can be independently disabled (output 3-stated) via IPD. When IPD is
set for both channels, the device enters a low-power standby mode. In this mode, the serial port must not
be operated faster than 39 kHz.
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