参数资料
型号: DS2165Q
厂商: DALLAS SEMICONDUCTOR
元件分类: Codec
英文描述: A/MU-LAW, ADPCM CODEC, PQCC28
封装: PLASTIC, LCC-28
文件页数: 12/18页
文件大小: 313K
代理商: DS2165Q
DS2165/DS2165Q
3 of 18
ALRST resets the algorithm coefficients for the selected channel to their initial values. ALRST will be
cleared by the device when the algorithm reset is complete.
PIN DESCRIPTION Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
1
RST
I
Reset. A high-low-high transition resets the algorithm. The device
should be reset on power-up and when changing to or from the
hardware mode.
2
3
TM0
TM1
I
Test Modes 0 and 1. Tie to VSS for normal operation.
4
5
6
7
8
9
A0
A1
A2
A3
A4
A5
I
Address Select. A0 = LSB; A5 = MSB; must match
address/command word to enable the serial port.
10
SPS
I
Serial Port Select. Tie to VDD to select the serial port; tie to VSS to
select the hardware mode.
11
MCLK
I
Master Clock. 10 MHz clock for the ADPCM processing engine;
may be asynchronous to SCLK, CLKX, and CLKY.
12
VSS
-
Signal Ground. 0.0 volts.
13
XIN
I
X Data In. Sampled on falling edge of CLKX during selected time
slots.
14
CLKX
I
X Data Clock. Data clock for the X side PCM interface; must be
synchronous with FSX.
15
FSX
I
X Frame Sync. 8 kHz frame sync for the X side PCM interface.
16
XOUT
O
X Data Output. Updated on rising edge of CLKX during selected
time slots.
17
SCLK
I
Serial Data Clock. Used to write to the serial port registers.
18
SDI
I
Serial Data In. Data for onboard control registers; sampled on the
rising edge of SCLK. LSB sent first.
19
CS
I
Chip Select. Must be low to write to the serial port.
20
YOUT
O
Y Data Output. Updated on rising edge of CLKY during selected
time slots.
21
FSY
I
Y Frame Sync. 8 kHz frame sync for the Y side PCM interface.
22
CLKY
I
Y Data Clock. Data clock for the Y side PCM interface; must be
synchronous with FSY.
23
YIN
I
Y Data In. Sampled on falling edge of CLKY during selected time
slots.
24
VDD
-
Positive Supply. 5.0 volts (or 3.0 volts for DS2165QL).
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