参数资料
型号: DS2181AQN+T&R
厂商: Maxim Integrated Products
文件页数: 5/32页
文件大小: 0K
描述: IC TXRX CEPT PRIMARY RATE 44PLCC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 500
类型: 收发器
驱动器/接收器数: 1/1
规程: CEPT
电源电压: 4.5 V ~ 5.5 V
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC(16.59x16.59)
包装: 带卷 (TR)
DS2181A
13 of 32
TSD INPUT TIMING Figure 7
CAS OUTPUT FORMAT IN TIMESLOT 16 Figure 8
FRAME 0
1
FRAME 1
FRAME 15
0000XYXX
ABCD for
Timeslot 1
ABCD for
timeslot 17
ABCD for
Timeslot 15
ABCD for
Timeslot 31
NOTE:
1. Timeslot 16 of frame 0 is reserved for the multiframe alignment word (0000), distant multiframe
alarm (Y) and extra bits (X-XX).
TINR: TRANSMIT INTERNATIONAL AND NATIONAL REGISTER Figure 9
(MSB)
(LSB)
INB
-
TRA
NB4
NB5
NB6
NB7
NB8
SYMBOL
POSITION
NAME AND DESCRIPTION
INB
TINR.7
International Bit. Inserted into the outgoing data stream when
TCR.4 = 1.
-
TINR.6
Reserved; must be 0 for proper operation.
TRA
TINR.5
Transmit Remote Alarm
0 = Normal operation; bit 3 of timeslot 0 in non-alignment frame
clear.
1 = Alarm condition; bit 3 of timeslot 0 in non-align frames set.
NB4
TINR.4
Transmit National Bits. Inserted into the outgoing data stream at
TPOS and TNEG when TCR.3 = 1.
NB5
TINR.3
NB6
TINR.2
NB7
TINR.1
NB8
TINR.0
TRANSMIT INTERNATIONAL AND NATIONAL DATA
Bit 1 of timeslot 0 in all frames is known as the international bit. When TCR.4 = 1, the transmitted
international bit is sourced from TINR.7. When TCR.4 = 0, the transmitted international bit is sampled at
TIND during the first bit period of each frame. The international bit positions in all outgoing frames
except 13 and 15 are replaced by CRC4 code words and the CRC4 multiframe alignment signal when
CCR.3 = 1.
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