参数资料
型号: DS21FF44
厂商: Maxim Integrated Products
文件页数: 31/117页
文件大小: 0K
描述: IC FRAMER E1 4X4 16CH 300-BGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 40
控制器类型: E1 调帧器
接口: 并行/串行
电源电压: 2.97 V ~ 3.63 V
电流 - 电源: 300mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 300-BBGA
供应商设备封装: 300-PBGA(27x27)
包装: 管件
DS21FT44/DS21FF44
20 of 117
7. DS21Q44 PIN FUNCTION DESCRIPTION
This section describes the signals on the DS21Q44 die. Signals that are not bonded out or have limited
functionality in the DS21FT44 and DS21FF44 are noted in italics.
TRANSMIT SIDE PINS
Signal Name:
TCLK
Signal Description:
Transmit Clock
Signal Type:
Input
A 2.048MHz primary clock. Used to clock data through the transmit side formatter.
Signal Name:
TSER
Signal Description:
Transmit Serial Data
Signal Type:
Input
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is
disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
Signal Name:
TCHCLK
Signal Description:
Transmit Channel Clock
Signal Type:
Output
A 256kHz clock that pulses high during the LSB of each channel. Synchronous with TCLK when the
transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is
enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS = 1
(DS21Q43 emulation). This signal is not bonded out in the DS21FF44/DS21FT44.
Signal Name:
TCHBLK
Signal Description:
Transmit Channel Block
Signal Type:
Output
A user-programmable output that can be forced high or low during any of the 32 E1 channels.
Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK
when the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all E1 channels are used such as Fractional E1, 384kbps (H0),
768kbps, 1920kbps (H12) or ISDN–PRI. Also useful for locating individual channels in drop-and-insert
applications, for external per-channel loopback, and for per-channel conditioning. See Section 16 for
details. This signal is not bonded out in the DS21FF44/DS21FT44.
Signal Name:
TSYSCLK
Signal Description:
Transmit System Clock
Signal Type:
Input
1.544MHz or 2.048MHz clock. Only used when the transmit side elastic store function is enabled. Should
be connected low in applications that do not use the transmit side elastic store. Can be burst at rates up to
8.192MHz. This pin is connected to the RSYSCLK signal in the DS21FF44/DS21FT44.
Signal Name:
TLCLK
Signal Description:
Transmit Link Clock
Signal Type:
Output
4kHz to 20kHz demand clock for the TLINK input. See Section 18 for details. This signal is not bonded
out in the DS21FF44/DS21FT44.
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