参数资料
型号: DS21FF44
厂商: Maxim Integrated Products
文件页数: 90/117页
文件大小: 0K
描述: IC FRAMER E1 4X4 16CH 300-BGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 40
控制器类型: E1 调帧器
接口: 并行/串行
电源电压: 2.97 V ~ 3.63 V
电流 - 电源: 300mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 300-BBGA
供应商设备封装: 300-PBGA(27x27)
包装: 管件
DS21FT44/DS21FF44
74 of 117
HSR: HDLC STATUS REGISTER (Address = B1 Hex)
(MSB)
(LSB)
RPE
RPS
RHALF
RNE
THALF
TNF
TMEND
SYMBOL
POSITION
NAME AND DESCRIPTION
—HSR.7
Not Assigned. Should be set to zero.
RPE
HSR.6
Receive Packet End. Set when the HDLC controller detects
either the finish of a valid message (i.e., CRC check complete)
or when the controller has experienced a message fault such as
a CRC checking error, or an overrun condition, or an abort has
been seen. The setting of this bit prompts the user to read the
RHIR register for details.
RPS
HSR.5
Receive Packet Start. Set when the HDLC controller detects
an opening byte. The setting of this bit prompts the user to read
the RHIR register for details.
RHALF
HSR.4
Receive FIFO Half Full. Set when the receive 64 byte FIFO
fills beyond the half-way point. The setting of this bit prompts
the user to read the RHIR register for details.
RNE
HSR.3
Receive FIFO Not Empty. Set when the receive 64 byte FIFO
has at least 1 byte available for a read. The setting of this bit
prompts the user to read the RHIR register for details.
THALF
HSR.2
Transmit FIFO Half Empty. Set when the transmit 64 byte
FIFO empties beyond the half-way point. The setting of this bit
prompts the user to read the THIR register for details.
TNF
HSR.1
Transmit FIFO Not Full. Set when the transmit 64 byte FIFO
has at least 1 byte available. The setting of this bit prompts the
user to read the THIR register for details.
TMEND
HSR.0
Transmit Message End. Set when the transmit HDLC
controller has finished sending a message. The setting of this
bit prompts the user to read the THIR register for details.
Note: The RPE, RPS, and TMEND bits are latched and are cleared when read.
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