参数资料
型号: DS21Q41BT
厂商: Maxim Integrated Products
文件页数: 29/61页
文件大小: 0K
描述: IC FRAMER T1 QUAD 128-TQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 72
控制器类型: T1 调帧器
接口: 并行/串行
电源电压: 4.5 V ~ 5.5 V
电流 - 电源: 30mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-LQFP(14x20)
包装: 管件
DS21Q41B
35 of 61
RS1 TO RS12: RECEIVE SIGNALING REGISTERS (Address=60 to 6B Hex)
(MSB)
(LSB)
A(8)
A(7)
A(6)
A(5)
A(4)
A(3)
A(2)
A(1)
RS1 (60)
A(16)
A(15)
A(14)
A(13)
A(12)
A(11)
A(10)
A(9)
RS2 (61)
A(24)
A(23)
A(22)
A(21)
A(20)
A(19)
A(18)
A(17)
RS3 (62)
B(8)
B(7)
B(6)
B(5)
B(4)
B(3)
B(2)
B(1)
RS4 (63)
B(16)
B(15)
B(14)
B(13)
B(12)
B(11)
B(10)
B(9)
RS5 (64)
B(24)
B(23)
B(22)
B(21)
B(20)
B(19)
B(18)
B(17)
RS6 (65)
A/C(8)
A/C(7)
A/C(6)
A/C(5)
A/C(4)
A/C(3)
A/C(2)
A/C(1)
RS7 (66)
A/C(16)
A/C(15)
A/C(14)
A/C(13)
A/C(12)
A/C(11)
A/C(10)
A/C(9)
RS8 (67)
A/C(24)
A/C(23)
A/C(22)
A/C(21)
A/C(20)
A/C(19)
A/C(18)
A/C(17)
RS9 (68)
B/D(8)
B/D(7)
B/D(6)
B/D(5)
B/D(4)
B/D(3)
B/D(2)
B/D(1)
RS10 (69)
B/D(16)
B/D(15)
B/D(14)
B/D(13)
B/D(12)
B/D(11)
B/D(10)
B/D(9)
RS11 (6A)
B/D(24)
B/D(23)
B/D(22)
B/D(21)
B/D(20)
B/D(19)
B/D(18)
B/D(17)
RS12 (6B)
SYMBOL
POSITION
NAME AND DESCRIPTION
D(24)
RS12.7
Signaling Bit D in Channel 24
A(1)
RS1.0
Signaling Bit A in Channel 1
Each Receive Signaling Register (RS1 to RS12) reports the incoming robbed bit signaling from eight
DS0 channels. In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and
D). In the D4 framing mode, there are only two signaling bits per channel (A and B). In the D4 framing
mode, the DS21Q41B will replace the C and D signaling bit positions with the A and B signaling bits
from the previous multiframe. Hence, whether the DS21Q41B is operated in either framing mode, the
user needs only to retrieve the signaling bits every 3 ms. The bits in the Receive Signaling Registers are
updated on multiframe boundaries in both framing modes so the user can utilize the Receive Multiframe
Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the signaling bits. The
Receive Signaling Registers are frozen and not updated during a loss of sync condition (SR1.0=1). They
will contain the most recent signaling information before the “OOF” occurred.
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