参数资料
型号: DS21Q41BT
厂商: Maxim Integrated Products
文件页数: 30/61页
文件大小: 0K
描述: IC FRAMER T1 QUAD 128-TQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 72
控制器类型: T1 调帧器
接口: 并行/串行
电源电压: 4.5 V ~ 5.5 V
电流 - 电源: 30mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-LQFP(14x20)
包装: 管件
DS21Q41B
36 of 61
TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address=70 to 7B Hex)
(MSB)
(LSB)
A(8)
A(7)
A(6)
A(5)
A(4)
A(3)
A(2)
A(1)
TS1 (70)
A(16)
A(15)
A(14)
A(13)
A(12)
A(11)
A(10)
A(9)
TS2 (71)
A(24)
A(23)
A(22)
A(21)
A(20)
A(19)
A(18)
A(17)
TS3 (72)
B(8)
B(7)
B(6)
B(5)
B(4)
B(3)
B(2)
B(1)
TS4 (73)
B(16)
B(15)
B(14)
B(13)
B(12)
B(11)
B(10)
B(9)
TS5 (74)
B(24)
B(23)
B(22)
B(21)
B(20)
B(19)
B(18)
B(17)
TS6 (75)
A/C(8)
A/C(7)
A/C(6)
A/C(5)
A/C(4)
A/C(3)
A/C(2)
A/C(1)
TS7 (76)
A/C(16)
A/C(15)
A/C(14)
A/C(13)
A/C(12)
A/C(11)
A/C(10)
A/C(9)
TS8 (77)
A/C(24)
A/C(23)
A/C(22)
A/C(21)
A/C(20)
A/C(19)
A/C(18)
A/C(17)
TS9 (78)
B/D(8)
B/D(7)
B/D(6)
B/D(5)
B/D(4)
B/D(3)
B/D(2)
B/D(1)
TS10 (79)
B/D(16)
B/D(15)
B/D(14)
B/D(13)
B/D(12)
B/D(11)
B/D(10)
B/D(9)
TS11 (7A)
B/D(24)
B/D(23)
B/D(22)
B/D(21)
B/D(20)
B/D(19)
B/D(18)
B/D(17)
TS12 (7B)
SYMBOL
POSITION
NAME AND DESCRIPTION
D(24)
TS12.7
Signaling Bit D in Channel 24
A(1)
TS1.0
Signaling Bit A in Channel 1
Each Transmit Signaling Register (TS1 to TS12) contains the Robbed Bit signaling for eight DS0
channels that will be inserted into the outgoing stream if enabled to do so via TCR1.4. In the ESF framing
mode, there can be up to four signaling bits per channel (A, B, C, and D). On multiframe boundaries, the
DS21Q41B will load the values present in the Transmit Signaling Register into an outgoing signaling
shift register that is internal to the device. The user can utilize the Transmit Multiframe Interrupt in Status
Register 2 (SR2.6) to know when to update the signaling bits. In the ESF framing mode, the interrupt will
come every 3 ms and the user has a full 3 ms to update the TSRs. In the D4 framing mode, there are only
two framing bits per channel (A and B). However in the D4 framing mode, the DS21Q41B uses the C and
D-bit positions as the A and B bit positions for the next multiframe. The DS21Q41B will load the values
in the TSRs into the outgoing shift register every other D4 multiframe.
8.0 SPECIAL TRANSMIT SIDE REGISTERS
There is a set of seven registers in the DS21Q41B that can be used to custom tailor the data that is to be
transmitted onto the T1 line, on a channel by channel basis. Each of the 24 T1 channels can be either
forced to be transparent or to have a user defined idle code inserted into them. Each of these special
registers is defined below.
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