参数资料
型号: DS21Q55DK
厂商: Maxim Integrated Products
文件页数: 2/32页
文件大小: 0K
描述: KIT DESIGN FOR DS21Q55
标准包装: 1
类型: 收发器
适用于相关产品: DS21Q55
所含物品: 主板,子卡,软件和文档
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
TABLE OF CONTENTS
COMPONENT LIST .....................................................................................................................3
BOARD FLOORPLAN.................................................................................................................4
ERRATA ......................................................................................................................................4
BASIC OPERATION....................................................................................................................4
H ARDWARE C ONFIGURATION .....................................................................................................................4
Using the DK101 Processor Board: ..................................................................................................................... 4
Using the DK2000 Processor Board: ................................................................................................................... 4
General ................................................................................................................................................................. 5
Miscellaneous ....................................................................................................................................................... 5
Q UICK S ETUP (D EMO M ODE ).....................................................................................................................5
Q UICK S ETUP (R EGISTER V IEW ) ........................................................................................................5
ADDRESS MAP ..........................................................................................................................6
FPGA R EGISTER M AP ........................................................................................................................7
ID REGISTERS............................................................................................................................7
CONTROL REGISTERS..............................................................................................................8
FPGA CONTROL EXAMPLES..................................................................................................15
DS21Q55 INFORMATION .........................................................................................................17
DS21Q55DK INFORMATION....................................................................................................17
TECHNICAL SUPPORT ............................................................................................................17
SCHEMATICS ...........................................................................................................................17
DOCUMENT REVISION HISTORY ...........................................................................................17
LIST OF TABLES
Table 1. Daughter Card Address Map........................................................................................................ 6
Table 2. FPGA Register Map ..................................................................................................................... 7
Table 3. TCLKx Source Definition .............................................................................................................. 8
Table 4. TSYSCLKx Source Definition ....................................................................................................... 9
Table 5. RSYSCLKx Source Definition....................................................................................................... 9
Table 6. RSYNCx Function Definition ...................................................................................................... 11
Table 7. TSERx Source Definition............................................................................................................ 12
Table 8. FPGA Configuration for Scenario #1 (Port 1, T1 Mode) .............................................................15
Table 9. FPGA Configuration for Scenario #2 (Port 1, T1 Mode) .............................................................16
Table 10. DS21Q55 Partial Configuration for Scenario #2 (Port 1, T1 Mode)..........................................16
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