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参数资料
| 型号： | DS2227-100 |
| 英文描述： | Flexible NV SRAM Stik |
| 中文描述： | 灵活的非易失SRAM装饰贴 |
| 文件页数： | 2/10页 |
| 文件大小： | 191K |
| 代理商： | DS2227-100 |
DS2227
2 of 10
select pins for each of the four banks of onboard memories (see Figure 1). For operation as a 512k x 8 NV
SRAM Stik, tie all data lines from each bank together (i.e., all D0s together, all D1s together, etc.). Read
enables and write enables are also tied together. For operation as a 256k x 16 NV SRAM Stik, tie the data
lines from two banks together. Chip enables, read enables, and write enables from these banks are also
tied together. Connection to the DS2227 is made by using an industry-standard, 72-position SIMM socket
DS9072-72V (AMP part number 821824-8). These SIMM sockets are also available in perpendicular,
inclined, or parallel mount, depending on the height available. See the DS907x SipStik
TM
connectors
available from Dallas Semiconductor.
READ MODE
The DS2227 executes a read cycle whenever
WE
(Write Enable) is inactive (high) and
CE
(Chip Enable)
and
OE
(Output Enable) are active (low). The unique address specified by the 17 address inputs (A
0
- A
16
)
defines which byte of data is to be accessed. Valid data will be available to the eight data I/O pins within
t
ACC
(access time) after the last address input signal is stable, providing that
CE
and
OE
access times are
also satisfied. If
OE
and
CE
times are not satisfied, then data access must be measured from the later
occurring signal (
CE
or
OE
) and the limiting parameter is either t
CO
for
CE
or t
OE
for
OE
rather than
address access.
WRITE MODE
The DS2227 is in the write mode whenever both
WE
and
CE
signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of
CE
or
WE
will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must
be kept valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time
(t
WR
) before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output bus has been enabled (
CE
and
OE
active)
then
WE
will disable the outputs to t
ODW
from its falling edge.
DATA RETENTION MODE
The DS2227 provides fully functional capability for V
CC
greater than 4.5 volts and guarantees write
protection for V
CC
less than 4.25 volts. Data is maintained in the absence of V
CC
without any additional
support circuitry. The DS2227 constantly monitors V
CC
. Should the supply voltage decay, the NV
SRAM automatically write-protects itself, all inputs become “don’t care” and all outputs become high
impedance. As V
CC
falls below approximately 3.0 volts, a power switching circuit connects a lithium
energy source to RAM to retain data. During power-up, when V
CC
rises above approximately 3.0 volts,
the power switching circuit connects the external V
CC
to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
exceeds 4.5 volts.
The DS2227 checks lithium status to warn of potential data loss. Each time that V
CC
power is restored to
the DS2227, the battery voltage is checked with a precision comparator. If the battery supply is less than
2.0 volts, the second memory access to the device is inhibited. Battery status can, therefore, be
determined by a three-step process. First, a read cycle is performed to any location in memory, in order to
save the contents of that location. A subsequent write cycle can then be executed to the same memory
location, altering data. If the next read cycle fails to verify the written data, then the battery voltage is less
than 2.0V and data is in danger of being corrupted.
The DS2227 also provides battery redundancy. In many applications data integrity is paramount. The
DS2227 provides two batteries for each SRAM and an internal isolation switch to select between them.
During battery backup, the battery with the highest voltage is selected for use. If one battery fails, the
other automatically takes over. The switch between batteries is transparent to the user.
相关PDF资料 |
PDF描述 |
|---|---|
| DS2227-120 | Flexible NV SRAM Stik |
| DS2227 | Flexible NV SRAM Stik |
| DS2229 | Word-Wide 8 Meg SRAM Stik |
| DS2252T | Secure Microcontroller Module |
| DS2282 | T1 FDL Controller/Monitor Stik |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2227-120 | 功能描述:IC NVSRAM 4MBIT 120NS 72SIMM RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘 供应商设备封装:8-DFN（2x3） 包装:管件 产品目录页面:1445 (CN2011-ZH PDF) |
| DS2227-70 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:Flexible NV SRAM Stik |
| DS2228-100 | 功能描述:静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| DS2229 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:Word-Wide 8 Meg SRAM Stik |
| DS2229-100 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x16 SRAM Module |
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