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参数资料
| 型号： | DS2408S+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/39页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH 8-CHAN ADDRESS 16SOIC |
| 标准包装： | 2,500 |
| 接口： | 1 线 |
| 输入/输出数： | 8 |
| 中断输出： | * |
| 电源电压： | 2.8 V ~ 5.25 V |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
| 包括： | * |
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DS2408
12 of 39
Control/Status Register
The data in this register reports status information, determines the function of the RSTZ pin and further
configures the device for conditional search. This register can only be written through the Write Condi-
tional Search Registers command.
Control/Status Register Bitmap
ADDR
b7
b6
b5
b4
b3
b2
b1
b0
008Dh
VCCP
0
PORL
ROS
CT
PLS
This register is read/write. Without VCC supply, this register reads 08h after a power-on reset. The func-
tional assignments of the individual bits are explained in the table below. Bits 4 to 6 have no function;
they will always read 0 and cannot be set to 1.
Control/Status Register Details
BIT DESCRIPTION
BIT(S)
DEFINITION
PLS: Pin or Activity
Latch Select
b0
Selects either the PIO pins or the PIO activity latches as input for the
conditional search.
0: pin selected (default)
1: activity latch selected
CT: Conditional Search
Logical Term
b1
Specifies whether the data of two or more channels needs to be OR’ed
or AND’ed to meet the qualifying condition for the device to respond to a
conditional search. If only a single channel is selected in the channel
selection mask (008Bh) this bit is a don't care.
0: bitwise OR (default)
1: bitwise AND
ROS: RSTZ Pin Mode
Control
b2
Configures RSTZ as either RST input or STRB output
0: configured as RST input (default)
1: configured as STRB output
PORL: Power-On Reset
Latch
b3
Specifies whether the device has performed a power-on reset. This bit
can only be cleared to 0 under software control. As long as this bit is 1
the device will always respond to a conditional search.
VCCP: VCC Power
Status (Read-Only)
b7
For VCC powered operation the VCC pin needs to be tied to a voltage
source ≥ VPUP.
0: VCC pin is grounded
1: VCC -powered operation
The interaction of the various signals that determine whether the device responds to a conditional search
is illustrated in Figure 7. The selection mask SM selects the participating channels. The polarity selection
SP determines for each channel whether the channel signal needs to be 1 or 0 to qualify. The PLS bit
determines whether all channel signals are taken from the activity latches or I/O pins. The signals of all
channels are fed into an AND gate as well as an OR gate. The CT bit finally selects the AND’ed or
OR’ed result as the conditional search response signal CSR.
Note on CT bit:
OR
The qualifying condition is met if the input (pin state or activity latch) for one or more selected
channels matches the corresponding polarity.
AND For the qualifying condition to be met, the input (pin state or activity latch) for every selected
channel must match the corresponding polarity.
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