DS2411
3 of 11
PARAMETER
I/O PIN, 1-Wire RESET, PRESENCE DETECT CYCLE
Reset Low Time
SYMBOL
CONDITIONS
MIN
MAX UNITS
Standard speed
Overdrive speed
Standard speed
Overdrive V
CC
≥
2.2V
Overdrive V
CC
≥
1.5V
Standard speed
Overdrive V
CC
≥
2.2V
Overdrive V
CC
≥
1.5V
Standard speed (Note 10, 3)
Overdrive speed (Note 10, 3)
Standard speed (Note 1)
Overdrive V
CC
≥
2.2V (Note 1)
Overdrive V
CC
≥
1.5V (Note 1)
480
60
15
2
2
60
8
8
0.4
0.05
60
6
8.5
640
80
60
6
8.5
240
24
30
8
1
75
10
10
t
RSTL
μ
s
Presence-Detect High Time
t
PDH
μ
s
Presence-Detect Low Time
t
PDL
μ
s
Presence-Detect Fall Time
t
FPD
μ
s
Presence-Detect Sample
Time
t
MSP
μ
s
I/O PIN, 1-Wire WRITE
Standard speed (Notes 1, 13)
Overdrive V
CC
≥
2.2V (Notes 1,
13)
Overdrive V
CC
≥
1.5V (Notes 1,
13)
Standard speed (Notes 1, 11, 13)
Overdrive speed (Notes 1, 11, 13)
60
120
6
16
Write-0 Low Time
t
W0L
8
16
μ
s
5
1
15 -
2 -
Write-1 Low Time
t
W1L
μ
s
I/O PIN, 1-Wire READ
Standard speed (Notes 1, 11)
Overdrive speed (Notes 1, 11)
Standard speed (Notes 1, 12)
Overdrive speed (Notes 1, 12)
5
1
15 -
2 -
15
2
Read Low Time
t
RL
μ
s
t
RL
+
t
RL
+
Read Sample Time
t
MSR
μ
s
Note 1:
Note 2:
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the
system and 1-Wire recovery times. The specified value here applies to systems with only
one device and with the minimum 1-Wire recovery times. For more heavily loaded
systems, an active pullup such as that found in the DS2480B may be required. Minimum
allowable pullup resistance is slightly greater than the value necessary to produce the
absolute maximum current (20mA) during 1-Wire low times at V
PUP
= 5.25V assuming
V
OL
= 0V.
Not production tested.
V
TL
and V
TH
are functions of V
CC
and temperature.
Voltage below which during a falling edge on I/O, a logic ‘0’ is detected.
Voltage above which during a rising edge on I/O, a logic ‘1’ is detected.
After V
TH
is crossed during a rising edge on I/O, the voltage on I/O has to drop by V
HY
to
be detected as logic ‘0’.
The I-V characteristic is linear for voltages less than 1V.
The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been reached
on the previous edge.
Interval during the negative edge on I/O at the beginning of a presence-detect pulse
between the time at which the voltage is 90% of V
PUP
and the time at which the voltage is
10% of V
PUP
.
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: