参数资料
型号: DS2436Z
厂商: DALLAS SEMICONDUCTOR
元件分类: Memory IC:Other
英文描述: SPECIALTY MEMORY CIRCUIT, PDSO8
封装: 0.150 INCH, SOIC-8
文件页数: 8/29页
文件大小: 505K
代理商: DS2436Z
DS2436
16 of 29
1-WIRE CRC CODE Figure 6
1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master and one or more slaves. The DS2436 behaves
as a slave. All data is communicated LSB first. The discussion of this bus system is broken down into
three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and
timing).
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain or three-state outputs. The 1-Wire port of the DS2436 (DQ pin) is open drain with an internal circuit
equivalent to that shown in Figure 7. A multidrop bus consists of a 1-Wire bus with multiple slaves
attached. The 1-Wire bus requires a pullup resistor of approximately 5 k
.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state for the transaction to resume. Infinite recovery time can occur between bits
so long as the 1-Wire bus is in the inactive (HIGH) state during the recovery period. If this does not occur
and the bus is left low for more than 480
s, all components on the bus will be reset.
TRANSACTION SEQUENCE
The protocol for accessing the DS2436 via the 1-Wire port is as follows:
§ Initialization
§ ROM Function Command
§ Memory Function Command
§ Transaction/Data
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
slave(s).
The presence pulse lets the bus master know that the DS2436 is on the bus and is ready to operate. For
more details, see the “1-Wire Signaling” section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the four ROM function commands. All
ROM function commands are 8 bits long. A list of these commands follows (refer to flowchart in Figure
5).
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