参数资料
型号: DS26334
英文描述: 3.3V, 16-Channel, E1/T1/J1 Short and Long-Haul Line Interface Unit
中文描述: 3.3V、16路、E1/T1/J1短/长程线路接口单元
文件页数: 66/115页
文件大小: 756K
代理商: DS26334
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
66 of 115
Register Name:
Register Description:
Register Address (LIUs 1-8):
Bit #
Name
IAISEL8
Default
Register Address (LIUs 9-16):
Bit #
Name
IAISEL16
Default
Bit 7-0: Individual AIS Enable During Loss
n
(IAISEL
n
).
When this bit is set Individual AIS Enable During loss is
enabled for the individual Receiver
n
and AIS is sent to the system side upon detection a LOS of signal. Note that if
the
GC
.AISEL register bit is set, the settings in this register will be ignored.
IAISEL
Individual AIS Select
05h
7
6
5
4
3
2
1
0
IAISEL7
0
IAISEL6
0
IAISEL5
0
IAISEL4
0
IAISEL3
0
IAISEL2
0
IAISEL1
0
0
25h
7
6
5
4
3
2
1
0
IAISEL15
0
IAISEL14
0
IAISEL13
0
IAISEL12
0
IAISEL11
0
IAISEL10
0
IAISEL9
0
0
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7 to 6: PLL Clock Input [1:0] (PCLKI[1:0]).
These bits select the input into to the PLL.
00 MCLK is used.
01 RCLK1 to 8 is used based on the selection in register
CCR.
10 RCLK9 to 16 is used based on the selection in register CCR.
11 Reserved.
Bit 5: T1/E1 Clock Enable (TECLKE).
When this bit is set the TECLK output is enabled. If not set TECLK will be
disabled and the TECLK output is a LOS output. TECLK requires PLLE to be set for correct functionality.
MC
Master Clock Select
06h
7
6
5
4
3
2
1
0
PCLKI1
0
PCLKI0
0
TECLKE
0
CLKAE
0
MPS1
0
MPS0
0
FREQS
0
PLLE
0
Bit 4: Clock A Enable (CLKAE).
When this bit is set the CLKA output is enabled. If not set CLKA will be disabled
and the CLKA output is a LOS output. CLKA requires PLLE to be set for correct functionality.
Bit 3 to 2: Master Period Select [1:0] (MPS[1:0]).
These bits MPS[1:0] selects the external MCLK frequency for
the DS26334. See
Table 6-16
for details. This register when written to will also controller functionality of channels 9
to 16.
Bit 1: Frequency Select(FREQS).
In conjunction with MPS[1:0] selects the external MCLK frequency for the
DS26334. If this bit is set the external Master clock can be 1.544 MHz or multiple thereof. If not set the external
master clock can be 2.048 MHz or multiple thereof. See
Table 6-16
for details. This register when written to will
also controller functionality of channels 9 to 16.
Bit 0: Phase Lock Loop Enable(PLLE).
When this bit is set the phase lock loop is enabled. If not set MCLK will
be the applied input clock.
相关PDF资料
PDF描述
DS26334G 3.3V, 16-Channel, E1/T1/J1 Short and Long-Haul Line Interface Unit
DS26334GN 3.3V, 16-Channel, E1/T1/J1 Short and Long-Haul Line Interface Unit
DS26503 T1/E1/J1 BITS Element
DS26503L T1/E1/J1 BITS Element
DS26503LN T1/E1/J1 BITS Element
相关代理商/技术参数
参数描述
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DS26334GA2 功能描述:电信集成电路 RoHS:否 制造商:STMicroelectronics 类型:Telecom IC - Various 工作电源电压:4.75 V to 5.25 V 电源电流: 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-100 封装:Tray