参数资料
型号: DS26503LN+
厂商: Maxim Integrated Products
文件页数: 110/122页
文件大小: 0K
描述: IC T1/E1/J1 BITS ELEMENT 64-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 160
类型: BITS 元件,多路复用器
PLL:
主要目的: T1/E1
输入: 时钟
输出: 时钟
电路数: 1
比率 - 输入:输出: 2:2
差分 - 输入:输出: 无/无
频率 - 最大: 6.312MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
产品目录页面: 1430 (CN2011-ZH PDF)
DS26503 T1/E1/J1 BITS Element
88 of 122
Register Name:
SR1
Register Description:
Status Register 1
Register Address:
14h
Bit #
7
6
5
4
3
2
1
0
Name
JALT
TCLE
TOCD
Default
0
HW
Mode
X
Bits 0, 3, 5, 6, 7: Unused, must be set = 0 for proper operation.
Bit 1: Transmit Open Circuit Detect Condition (TOCD). Set when the device detects that the TTIP and TRING outputs are
open-circuited. Note: This function not supported in transmit 6312kHz mode and is not guaranteed by production testing.
Bit 2: Transmit Current Limit Exceeded Condition (TCLE). Set when the current limiter is activated whether the current
limiter is enabled or not. This is set at approximately 50mA (RMS) on the network side of the transformer in E1 operating
modes and 70mA (RMS) on the network side of the transformer in T1 operating modes. These values are approximate and are
not guaranteed by production testing. Note: This function not supported in transmit CMI, 64kHz or 6312kHz mode.
Bit 4: Jitter Attenuator Limit Trip Event (JALT). Set when the jitter attenuator FIFO reaches to within 4 bits of its useful
limit. Will be cleared when read. Useful for debugging jitter-attenuation operation.
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