参数资料
型号: DS26503LN+
厂商: Maxim Integrated Products
文件页数: 67/122页
文件大小: 0K
描述: IC T1/E1/J1 BITS ELEMENT 64-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 160
类型: BITS 元件,多路复用器
PLL:
主要目的: T1/E1
输入: 时钟
输出: 时钟
电路数: 1
比率 - 输入:输出: 2:2
差分 - 输入:输出: 无/无
频率 - 最大: 6.312MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
产品目录页面: 1430 (CN2011-ZH PDF)
DS26503 T1/E1/J1 BITS Element
49 of 122
Table 9-2. E1 Alarm Criteria
ALARM
SET CRITERIA
CLEAR CRITERIA
ITU
SPEC.
RLOF
An RLOF condition exists on power-up
prior to initial synchronization, when a
resync criteria has been met, or when a
manual resync has been initiated via
E1RCR.0
RLOS
255 or 2048 consecutive zeros received as
determined by E1RCR.0
In 255-bit times, at least 32
ones are received
G.775/G.962
RRA
Bit 3 of non-align frame set to one for
three consecutive occasions
Bit 3 of non-align frame set to
zero for three consecutive
occasions
O.162
2.1.4
RUA1
Fewer than three zeros in two frames (512
bits)
More than two zeros in two
frames (512 bits)
O.162
1.6.1.2
RDMA
Bit 6 of time slot 16 in frame 0 has been
set for two consecutive multiframes
V52LNK
Two out of three Sa7 bits are zero
G.965
Register Name:
IDR
Register Description:
Device Identification Register
Register Address:
10h
Bit #
7
6
5
4
3
2
1
0
Name
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Default
0
1
N
HW
Mode
X
Bits 0 to 3:Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to display the die revision of the chip.
ID0 is the LSB of a decimal code that represents the chip revision.
Bits 4 to 7: Device ID (ID4 to ID7). The upper four bits of the IDR are used to display the DS26503 ID. The DS26503 ID is
0001.
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DS26504DK 功能描述:网络开发工具 DS26504 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V
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