参数资料
型号: DS26519DK
厂商: Maxim Integrated Products
文件页数: 13/42页
文件大小: 0K
描述: KIT DEMO FOR DS26519
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
设计资源: DS26519DK Gerber Files
标准包装: 1
主要目的: 电信,调帧器和线路接口装置(LIU)
已用 IC / 零件: DS26519
已供物品: 板,CD
DS26519DK
Register Name: CLKDIVIDE
Register Description: SYNC CLOCK DIVIDER
Register Offset: 0x011a
Bit #
Name
Default
7
B7
0
6
B6
0
5
B5
0
4
B4
0
3
B3
0
2
B2
0
1
B1
0
0
B0
0
Note: The SYNC SOURCE clock is divided by the value in this register to provide a local sync. For instance, for T1
a divisor of 193 is appropriate (C1H)
Register Name: SYNCSRC
Register Description: LOCAL SYNC CLOCK SOURCE AND NET SYNC SOURCE
Register Offset: 0x011b
Bit #
Name
Default
7
TSYNC1
0
6
RSYNC1
0
5
LOCAL
0
4
LOCAL
0
3
BPCLK1
0
2
OSC1
0
1
CLOCK1
0
0
CLOCK1
0
Note: A one written to the upper nibble connects internal net (sync) to respective source. A one written lower nibble
connects local sync generator to respective clock. Bit named LOCAL is a locally generated sync.
Register Name: TSYSCLKSRC1
Register Description: TSYSCLK SOURCE 1
Register Offset: 0x011c
Bit #
Name
Default
7
BPCLK1
0
6
CLOCK2
0
5
BPCLK1
0
4
CLOCK2
0
3
BPCLK1
0
2
CLOCK2
0
1
BPCLK1
0
0
CLOCK2
0
Note: A one written to bits 6 or 7 connects BPCLK1 or CLOCK2 to TSYSCLK4, respectively. Bits (4, 5), (2, 3), and
(0, 1) correspond similarly to TSYSCLK3, TSYSCLK2, and TSYSCLK1, respectively. CLOCK2 comes from
FPGA1.
Register Name: TSYSCLKSRC2
Register Description: TSYSCLK SOURCE 2
Register Offset: 0x011d
Bit #
Name
Default
7
BPCLK1
0
6
CLOCK2
0
5
BPCLK1
0
4
CLOCK2
0
3
BPCLK1
0
2
CLOCK2
0
1
BPCLK1
0
0
CLOCK2
0
Note: A one written to bits 6 or 7 connects BPCLK1 or CLOCK2 to TSYSCLK8, respectively. Bits (4, 5), (2, 3), and
(0, 1) correspond similarly to TSYSCLK7, TSYSCLK6, and TSYSCLK5, respectively. CLOCK2 comes from
FPGA1.
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