参数资料
型号: DS2703U+T&R
厂商: Maxim Integrated Products
文件页数: 3/20页
文件大小: 0K
描述: IC BATT AUTHENTICATE SHA-1 8UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 3,000
功能: 电池验证
电池化学: 锂离子(Li-Ion)
电源电压: 2.7 V ~ 5.5 V
工作温度: -20°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-uMAX
包装: 带卷 (TR)
DS2703 SHA-1 Battery Pack Authentication IC
AC ELECTRICAL CHARACTERISTICS
(V PULLUP = 2.7V to 5.5V, T A = -20°C to +70°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
THM Low Delay
Computation Delay Time
Computation Time
Programming Pulse Width
t TD
t D
t SHA
t PPW
(Note 11)
(Note 12)
(Note 12)
(Note 5)
100
17
15
15
μ s
μ s
ms
ms
Programming Pulse Rise Time
Programming Pulse Fall Time
Start-up Delay Time
t PPR
t PPF
t STRT
(Note 13)
0.5
0.5
5
5
100
μ s
μ s
ms
AC ELECTRICAL CHARACTERISTICS: 1-Wire INTERFACE
(V PULLUP = 2.7V to 5.5V, T A = -20°C to +70°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1-Wire INTERFACE REGULAR TIMING
Time Slot
Recovery Time
Write 0 Low Time
Write 1 Low Time
t SLOT
t REC
t LOW0
t LOW1
60
1
60
1
120
120
15
μ s
μ s
μ s
μ s
Read Data Valid Time
Reset Time High
t RDV
t RSTH
480
15
μ s
μ s
Reset Time Low
Presence Detect High
Presence Detect Low
t RSTL
t PDH
t PDL
480
15
60
960
60
240
μ s
μ s
μ s
1-Wire INTERFACE OVERDRIVE TIMING
Time Slot
Recovery Time
Write 0 Low Time
Write 1 Low Time
t SLOT
t REC
t LOW0
t LOW1
6
1
6
1
16
16
2
μ s
μ s
μ s
μ s
Read Data Valid Time
Reset Time High
t RDV
t RSTH
48
2
μ s
μ s
Reset Time Low
Presence Detect High
Presence Detect Low
t RSTL
t PDH
t PDL
48
2
8
80
6
24
μ s
μ s
μ s
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
V DQ – V THM . The THM pin must not be driven to a higher voltage than the DQ pin.
The application thermistor cannot exceed the R DQ-THM resistance range over operating temperature. If thermistor mode is not used in the application, it is
recommended that a 50K ? resistor be connected between DQ and THM pins instead.
Maximum leakage of DQ pin while in thermistor mode.
When performing a Lock Secret (0x6A), Set Overdrive (0x8B) or Clear Overdrive (0x8D) operation, there will be an increased operating current of I PGM-
IDLE during and after the program pulse until the next 1-Wire bus reset.
See Figure 11 for definitionof t PPR , t PPW , and t PPF.
All voltages referenced to VSS.
V DQ must be at least 3.0V when the 1-Wire bus is idle.
Drive strength at time=0 after Activate Thermistor command is sent to the DS2703.
Does not include capacitance referred from VB pin on initial power up.
EEPROM data read retention is four years at +50°C
Time from msb of Activate Thermistor command until THM pin is driven low internally.
Time from msb of Compute Next Secret or Compute MAC command.
Time after initial power up before the DS2703 will respond to communication. T STRT specifications are valid only if the capacitor on VB (C VB ) is 0.22μF.
Worst case 100ms delay based on maximum thermistor value of 500k ? .
The average current measured in Overdrive mode with minimum bus timings while the master issues: 1-Wire Reset, Skip ROM, Write Challenge, Write
0's repeatedly unil the end of measurement.
3 of 20
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